Latest Posts

Aug 19, 2021

The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.

  • PCIe 6.0
  • PCI Express 6.0
  • PAM4
  • PCIe FEC
  • Forward Error Correction
  • FLIT
Nov 30, 2020

Wow, 2020 sure has transformed the ways we connect, learn and innovate in industries around the world, and in our daily lives!

  • Standards & Compliance
  • PCI Express compliance
  • PCI-SIG Integrators List
  • PCIe 4.0
  • PCIe 3.0
Jun 22, 2020

For almost two decades, the PCI Express® (PCIe®) architecture has offered low latency and high bandwidth in support of next generation systems.

  • Systems & Applications
  • PCIe 6.0
  • PCI Express 6.0
  • PAM4
  • PCIe FEC
  • Forward Error Correction
  • FLIT
Feb 19, 2020

We are starting 2020 with the release of version 0.5 of the PCI Express® (PCIe®) 6.0 specification incorporating the significant member feedback received on version 0.3.

  • Standards & Compliance
  • PCIe 6.0
  • PCI Express 6.0
  • PAM4
  • PCIe FEC
  • Forward Error Correction
  • FLIT
  • PCI Express specification
May 19, 2019

I am pleased to announce that PCI Express® 5.0 specification, Version 1.0— reaching 32GT/s transfer rates—has been released to our members in less than 2 years.

  • Systems & Applications
  • PCI-SIG
  • PCIe 5.0
  • PCI Express 5.0
  • PCI-SIG Membership
Nov 08, 2018

The PCI-SIG Serial Enabling Workgroup (called the “SEG” for short) is the PCI-SIG workgroup charged with running the PCI Express® (PCIe®) compliance program.

  • Standards & Compliance
  • PCI-SIG
  • PCI-SIG Compliance
  • PCI-SIG Interoperability
  • PCI-SIG Integrators List