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The PCI-SIG® Developers Conference returned to Taipei, Taiwan for the first time since 2019 on Feb. 20-21 at the Taipei Marriott Hotel. With 674 total attendees, it was the highest-ever turnout for a DevCon.
- Standards and Compliance
- Developers Conference
- PCI-SIG DevCon
- PCI-SIG Compliance
- PCI-SIG Integrators List
It’s hard to believe it’s been 30 years since PCI-SIG® formed in 1992.
- Standards & Compliance
- Compliance
- PCI Express 5.0
- PCIe 5.0 Compliance
- PCI-SIG
- PCI-SIG Compliance
- PCI-SIG Integrators List
PCI-SIG® Compliance Workshop Updates: Workshop #118 Recap, PCIe 5.0 Specification Workshops and More
PCI-SIG® has continued to host PCI Express® (PCIe®) Compliance Workshops throughout 2021 as we recognize that they are an important member benefit.
- Standards & Compliance
- Compliance
- PCIe 5.0 specification
- PCIe 5.0
- PCI-SIG Integrators List
- PCI Express 5.0
I am excited to report that PCI-SIG has released PCIe 6.0 specification, version 0.9 to our members. This is a major milestone in our continued effort to double the data rate of the PCI Express® specifications while maintaining backwards compatibility.
- Standards & Compliance
- PCIe 6.0 specification
- PCIe 6.0
- PAM4
- PCIe FEC
- FLIT
- PCI Express specification
The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe FEC
- Forward Error Correction
- FLIT
By: Hope Bovenzi, Strategic Marketing, Astera Labs
- Signal Integrity
- automotive
- PCIe
- PCI Express
- PCIe Storage
- PCIe Retimer
- PCIe connectivity
- PCIe Bandwidth
- PCI-SIG Automotive Taskforce
With global health and safety concerns related to the Covid-19 pandemic still greatly limiting in-person events in 2021, PCI-SIG® continues to offer compliance workshop opportunities to our members virtually.
- Standards & Compliance
- PCIe 6.0 specification
- PAM4 signaling
- PCIe 6.0 architecture
- PCIe form factor
- FLIT Mode
- PCIe FEC
Wow, 2020 sure has transformed the ways we connect, learn and innovate in industries around the world, and in our daily lives!
- Standards & Compliance
- PCI Express compliance
- PCI-SIG Integrators List
- PCIe 4.0
- PCIe 3.0
The PCI Express® (PCIe®) 6.0 specification will feature two primary mechanisms to correct errors: Forward Error Correction (FEC) and Cyclic Redundancy Check (CRC). Each 256-byte FLIT comprises of 242 bytes of payload which are protected by 8 Bytes of CRC.
- Systems & Applications
- PCIe 6.0
- PCI Express 6.0
- PCIe FEC
One of the many new features included in the PCI Express® (PCIe®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.
- Systems & Applications
- PCIe 6.0
- PCI Express 6.0
- What is PAM4
- PAM4
- PCIe FEC
- Forward Error Correction