Latest Posts
By: Hope Bovenzi, Strategic Marketing, Astera Labs
- Signal Integrity
- automotive
- PCIe
- PCI Express
- PCIe Storage
- PCIe Retimer
- PCIe connectivity
- PCIe Bandwidth
- PCI-SIG Automotive Taskforce
The PCI Express® (PCIe®) 6.0 specification will provide multiple features, including Transaction Layer Packet (TLP) payload, encoding and decoding, shared credit pooling, Forward Error Correction (FEC), CRC error correction, and more.
- Standards & Compliance
- PCI-SIG Automotive Taskforce
With the widespread adoption of compute-intensive workloads – such as artificial intelligence and machine learning – in enterprise and cloud data centers, high-speed, low-latency interconnects like PCI Express® architecture are required to connect high-performance nodes.
- Standards & Compliance
- PCIe 4.0
- PCIe 5.0
- PCIe retimers
- PCIe redrivers
- PCIe 5.0 specification
The upcoming PCI Express® (PCIe®) 6.0 specification will continue PCI-SIG’s® longstanding history of innovation for the next generation of products to keep up with evolving needs in a wide range of markets.
- Systems & Applications
- PCIe 6.0
- PCI Express 6.0
- PCIe L0p
- PCIe low power state
PCI Express® (PCIe®) technology is the most important high-speed serial bus in servers. Due to its high bandwidth and low latency characteristics, PCI Express architecture is widely used in various server interconnect scenarios, such as:
- Signal Integrity
- PCIe 5.0
- PCI Express 5.0
- PCIe CEM
- PCIe Channel Loss