PCI-SIG® is comprised of multiple technical work groups (TWGs) that develop PCI Express® (PCIe®) technology. Work groups are open to all PCI-SIG member company representatives and allow companies to shape current and future PCIe specifications.

The PCI-SIG® Developers Conference returned to Taipei, Taiwan for the first time since 2019 on Feb. 20-21 at the Taipei Marriott Hotel. With 674 total attendees, it was the highest-ever turnout for a DevCon.

PCI-SIG® is comprised of multiple technical work groups (TWGs) that work towards the development of PCI Express® (PCIe®) technology. Work groups are open to all PCI-SIG member company representatives and allow companies to further the PCIe specifications.

In early 2022, PCI-SIG® released the full version of the PCI Express® (PCIe®) 6.0 specification.

In early 2022, PCI-SIG® released the full version of the PCI Express® (PCIe®) 6.0 specification.

It’s hard to believe it’s been 30 years since PCI-SIG® formed in 1992.

With the ever-growing importance of security, we continue to see strong industry interest in Integrity and Data Encryption (IDE). As with any new technology, questions have been raised and addressed through new errata.

Introduction

For nearly three decades, PCI Express® (PCIe®) technology has served as the de facto high bandwidth, low latency interconnect. As the industry evolves to meet the needs of data-intensive applications, the PCIe specification has kept pace, enabling future innovation.

We are pleased to commence 2022 on a high note with the official release of the PCI Express® (PCIe®) 6.0 specification to members.

Infographic of the PCIe 6.0 Architecture

PCI-SIG® has continued to host PCI Express® (PCIe®) Compliance Workshops throughout 2021 as we recognize that they are an important member benefit.

I am excited to report that PCI-SIG has released PCIe 6.0 specification, version 0.9 to our members. This is a major milestone in our continued effort to double the data rate of the PCI Express® specifications while maintaining backwards compatibility.

The CXL™ Consortium and PCI-SIG® are excited to announce a memorandum of understanding (MOU) between the two organizations.

The CXL™ Consortium and PCI-SIG® are excited to announce a memorandum of understanding (MOU) between the two organizations.

With the emergence of autonomous vehicles, AI-based advanced driver assistance systems (ADAS) and in-vehicle infotainment (IVI), today’s automobiles are becoming high-tech “servers on wheels.” PCI Express® (PCIe®) technology is expanding to become the interconnect of choice in automotive applicat

With the emergence of autonomous vehicles, AI-based advanced driver assistance systems (ADAS) and in-vehicle infotainment (IVI), today’s automobiles are becoming high-tech “servers on wheels.” PCI Express® (PCIe®) technology is expanding to become the interconnect of choice in automotive applicat

With the emergence of autonomous vehicles, AI-based advanced driver assistance systems (ADAS) and in-vehicle infotainment (IVI), today’s automobiles are becoming high-tech “servers on wheels.” PCI Express® (PCIe®) technology is expanding to become the interconnect of choice in automotive applicat

The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.

By: Hope Bovenzi, Strategic Marketing, Astera Labs

By: Hope Bovenzi, Strategic Marketing, Astera Labs

Mohiuddin Mazumder of Intel was honored at this year’s PCI-SIG US DevCon

Manisha Nilange of Intel was honored at this year’s PCI-SIG US DevCon

With global health and safety concerns related to the Covid-19 pandemic still greatly limiting in-person events in 2021, PCI-SIG^® continues to offer compliance workshop opportunities to our members virtually.

Many online resources cover the history and current state of industry development for the concept that, in Integrity and Data Encryption (IDE), we refer to as a Trusted Execution Environment (TEE).

With the widespread adoption of compute-intensive workloads – such as artificial intelligence and machine learning – in enterprise and cloud data centers, high-speed, low-latency interconnects like PCI Express^® architecture are required to connect high-performance nodes.

Despite the many challenges in 2020, we are proud to report that it has been a successful year for, PCI-SIG^®.  We continued the momentum started in 2019 with PCIe^® 4.0 Compliance Testing, continued work on the PCIe 6.0 specification, and brought our members new ways to engag

Wow, 2020 sure has transformed the ways we connect, learn and innovate in industries around the world, and in our daily lives!

Wow, 2020 sure has transformed the ways we connect, learn and innovate in industries around the world, and in our daily lives!

One of the many new features included in the PCI Express^® (PCIe^®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.

PCI-SIG^® has shifted to virtual events for the 2020 calendar year and our first major members event was the Virtual PCI-SIG Developers Conference.

For almost two decades, the PCI Express^® (PCIe^®) architecture has offered low latency and high bandwidth in support of next generation systems.

At this year’s Open Compute Project Global Summit in San Jose on March 4 -5, attendees will have the opportunity to learn how PCI Express^® (PCIe^®) specifications enable OCP systems today and how newer versions of

We are starting 2020 with the release of version 0.5 of the PCI Express^® (PCIe^®) 6.0 specification incorporating the significant member feedback received on version 0.3.

The Internet of Things (IoT) Industry is rapidly growing in popularity and breadth of applications.

The Internet of Things (IoT) Industry is rapidly growing in popularity and breadth of applications.

According to Tractica, Artificial Intelligence (AI) and Machine Learning (ML) markets are set to grow to $118.6 billion by 2025—as  these new technologies are becoming the heart of our digital lives.

Our PCI-SIG^® members have been hard at work. In 2017, we delivered PCI Express^® 4.0 with its 16 GT/s, while also diving headfirst into PCI Express 5.0 development – first announced at our annual PCI-SIG DevCon in June 2017.

PCI Express^® (PCIe^®) technology is deployed worldwide by PCI-SIG member companies, so it only makes sense that PCI-SIG^® travels around the globe too.

Retimers and redrivers have enabled longer physical channels in servers and storage systems since Peripheral Component Interface Express (PCIe^®) 3.0 specification was first introduced almost 10 years ago.

Earlier this month, I attended another eventful Flash Memory Summit (FMS) and I am pleased to say that PCI Express^® (PCIe^®) was around every corner at this year’s event.

This year’s Flash Memory Summit (FMS) is coming up on August 6. As PCI Express technologies continue to evolve and make strides in the industry, PCI-SIG^® is excited to highlight our participation in the growth of flash storage.

PCI-SIG^® is proud to announce that we have established a working relationship with DMTF to simplify hardware management.

PCI-SIG^® is proud to announce that we have established a working relationship with DMTF to simplify hardware management.

This June 18-19, PCI-SIG and its 800+ member companies return to the Santa Clara Convention Center for the largest member event of the year: the Annual Members Meeting and Developers Conference.

PCI-SIG has built its reputation on delivering high quality PCI Express^® (PCIe) specifications that have doubled bandwidth on average every three years, while maintaining full backwards compatibility with prior generations.

PCI-SIG has built its reputation on delivering high quality PCI Express^® (PCIe) specifications that have doubled bandwidth on average every three years, while maintaining full backwards compatibility with prior generations.

his year, I was lucky enough to be able to attend and present at the Open Compute Project Summit and though it has come and gone by now, I’m already looking forward to the next one! 

Our PCI-SIG^® members have been hard at work. In 2017, we delivered PCI Express^® 4.0 with its 16 GT/s, while also diving headfirst into PCI Express 5.0 development – first announced at our annual PCI-SIG DevCon in June 2017.

The PCI-SIG Serial Enabling Workgroup (called the “SEG” for short) is the PCI-SIG workgroup charged with running the PCI Express^® (PCIe^®) compliance program.

By now, you probably know about the PCI-SIG Developers Conference which we hold in Santa Clara each year – a free event for our 750+ member companies with four tracks of presentations over two days.

PCI Express^® – also known as PCIe – used to get a bad rap for being power hungry on servers and PCs. But I’m happy to say that this is no longer the case. Are you aware that PCIe today is extremely power efficient with built-in low power features?

Whew, what a week! That’s another PCI-SIG Developers Conference in the books though.

After successfully releasing PCIe^® 4.0 Specification Version 1.0 last October, the members of the PCI-SIG^® have been heads down and hard at work to ensure PCIe 5.0 specification is made a reality by 2019.

I recently attended the OCP Summit for the first time and I was impressed by the size of this growing event. The San Jose Convention Center was packed with industry experts – all eager to discuss how to move the Open Compute Project (OPC) forward.

I’m pleased to share that PCI-SIG has released the PCIe 4.0 Specification Version 1.0 and it is now available for download on our website.