The PCI-SIG® Developers Conference returned to Taipei, Taiwan for the first time since 2019 on Feb. 20-21 at the Taipei Marriott Hotel. With 674 total attendees, it was the highest-ever turnout for a DevCon.

In early 2022, PCI-SIG® released the full version of the PCI Express® (PCIe®) 6.0 specification.

Around the World with PCI-SIG: Join Us at the 2022 International DevCons

By Richard Solomon, PCI-SIG Vice President and Developers Conference Chair

By Scott Knowlton and Mihaela Erler, PCI-SIG MWG Co-Chairs

The PCI-SIG® Board of Directors honored three individuals for their years of service and contributions to the development and expansion of PCI Express® (PCIe®) technology during the PCI-SIG US DevCon 2022 on June 21-22 in

During the PCI-SIG® US DevCon 2022, the PCI-SIG Board of Directors surprised two individuals for their years of service and contributions to the development and expansion of PCI Express® (PCIe®) technology.

It’s hard to believe it’s been 30 years since PCI-SIG® formed in 1992.

Introduction

For nearly three decades, PCI Express® (PCIe®) technology has served as the de facto high bandwidth, low latency interconnect. As the industry evolves to meet the needs of data-intensive applications, the PCIe specification has kept pace, enabling future innovation.

We are pleased to commence 2022 on a high note with the official release of the PCI Express® (PCIe®) 6.0 specification to members.

Infographic of the PCIe 6.0 Architecture

I am excited to report that PCI-SIG has released PCIe 6.0 specification, version 0.9 to our members. This is a major milestone in our continued effort to double the data rate of the PCI Express® specifications while maintaining backwards compatibility.

With the emergence of autonomous vehicles, AI-based advanced driver assistance systems (ADAS) and in-vehicle infotainment (IVI), today’s automobiles are becoming high-tech “servers on wheels.” PCI Express® (PCIe®) technology is expanding to become the interconnect of choice in automotive applicat

The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.

Mohiuddin Mazumder of Intel was honored at this year’s PCI-SIG US DevCon

Manisha Nilange of Intel was honored at this year’s PCI-SIG US DevCon

Many online resources cover the history and current state of industry development for the concept that, in Integrity and Data Encryption (IDE), we refer to as a Trusted Execution Environment (TEE).

One of the many new features included in the PCI Express^® (PCIe^®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.

PCI-SIG^® has shifted to virtual events for the 2020 calendar year and our first major members event was the Virtual PCI-SIG Developers Conference.

For almost two decades, the PCI Express^® (PCIe^®) architecture has offered low latency and high bandwidth in support of next generation systems.

We are starting 2020 with the release of version 0.5 of the PCI Express^® (PCIe^®) 6.0 specification incorporating the significant member feedback received on version 0.3.

The first installment of the PCI-SIG^® educational webinar series, “Retimers to the Rescue: PCI Express^® Specifications Reach Their Full Potential” premiered on October 9, 2019.

Retimers and redrivers have enabled longer physical channels in servers and storage systems since Peripheral Component Interface Express (PCIe^®) 3.0 specification was first introduced almost 10 years ago.

I am happy to share that PCI-SIG^® has begun developing the PCI Express^® (PCIe^®) 6.0 specification, targeted for release in 2021.

PCI-SIG^® is proud to announce that we have established a working relationship with DMTF to simplify hardware management.

This is already shaping up to be a busy year for PCI-SIG^® with the pending release of the PCI Express^® 5.0 specification targete

I’m happy to share that 2018 has been another productive year for PCI-SIG. In addition to significant progress in our specification development and compliance work, we also continued to provide educational resources to our members and the industry.

The PCI-SIG Serial Enabling Workgroup (called the “SEG” for short) is the PCI-SIG workgroup charged with running the PCI Express^® (PCIe^®) compliance program.

By now, you probably know about the PCI-SIG Developers Conference which we hold in Santa Clara each year – a free event for our 750+ member companies with four tracks of presentations over two days.

PCI Express^® – also known as PCIe – used to get a bad rap for being power hungry on servers and PCs. But I’m happy to say that this is no longer the case. Are you aware that PCIe today is extremely power efficient with built-in low power features?

Press conference on June 5 to announce PCIe 5.0 spec updates