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Sep 19, 2023

Author’s Note: This blog discusses new functionality introduced in the PCIe 6.0 specification, but please note that the PCIe 6.0.1 and PCIe 6.1 specification revisions have been published.

  • PCI Express Specification
  • PCI Express 6.0 Specification
  • PCIe 6.0 specification
  • PCI Express 6.0
  • PCI Express 6.0 Forward Error Correction
  • PCIe 6.0 FEC
  • FLIT Mode
Apr 13, 2023

The PCI-SIG® Members Forum is a resource for members to ask a variety of technical questions about PCI Express® (PCIe®) specifications and applications.

  • PCI-SIG Membership
  • PCI-SIG
  • PCI-SIG Work Groups
  • PCI Express compliance
  • PCIe Specification
  • PCIe Technology
Mar 29, 2023

In 2022, PCI-SIG® introduced PCI Express® (PCIe®) 5.0 Compliance Testing to members. PCIe 5.0 specification official testing includes a maximum link speed of 32 GT/s.

  • Standards and Compliance
  • PCI Express 5.0
  • PCI Express compliance
  • PCIe 5.0 Compliance
  • PCI-SIG Compliance
Dec 14, 2021

PCI-SIG® built upon our momentum from 2020 with another successful year in 2021. From progress on the PCIe 5.0 architecture compliance program to the impending release of the PCIe 6.0 specification, we have hit many exciting milestones.

  • Standards & Compliance
  • PCI Express 5.0
  • PCI Express 6.0
  • PCI Express 6.0 Specification
  • PCI Express compliance
  • PCI Express specification
  • PCI-SIG
  • PCI-SIG Compliance
  • PCI-SIG Membership
  • PCIe 5.0 specification
  • PCIe 6.0 specification
Oct 06, 2021

I am excited to report that PCI-SIG has released PCIe 6.0 specification, version 0.9 to our members. This is a major milestone in our continued effort to double the data rate of the PCI Express® specifications while maintaining backwards compatibility.

  • Standards & Compliance
  • PCIe 6.0 specification
  • PCIe 6.0
  • PAM4
  • PCIe FEC
  • FLIT
  • PCI Express specification
Aug 19, 2021

The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.

  • PCIe 6.0
  • PCI Express 6.0
  • PAM4
  • PCIe FEC
  • Forward Error Correction
  • FLIT
Apr 09, 2021

With global health and safety concerns related to the Covid-19 pandemic still greatly limiting in-person events in 2021, PCI-SIG® continues to offer compliance workshop opportunities to our members virtually.

  • Standards & Compliance
  • PCIe 6.0 specification
  • PAM4 signaling
  • PCIe 6.0 architecture
  • PCIe form factor
  • FLIT Mode
  • PCIe FEC
Apr 09, 2021

With global health and safety concerns related to the Covid-19 pandemic still greatly limiting in-person events in 2021, PCI-SIG® continues to offer compliance workshop opportunities to our members virtually.

  • Standards & Compliance
  • PCIe 6.0 specification
  • PAM4 signaling
  • PCIe 6.0 architecture
  • PCIe form factor
  • FLIT Mode
  • PCIe FEC
Nov 30, 2020

Wow, 2020 sure has transformed the ways we connect, learn and innovate in industries around the world, and in our daily lives!

  • Standards & Compliance
  • PCI Express compliance
  • PCI-SIG Integrators List
  • PCIe 4.0
  • PCIe 3.0
Sep 28, 2020

The PCI Express® (PCIe®) 6.0 specification will feature two primary mechanisms to correct errors: Forward Error Correction (FEC) and Cyclic Redundancy Check (CRC). Each 256-byte FLIT comprises of 242 bytes of payload which are protected by 8 Bytes of CRC.

  • Systems & Applications
  • PCIe 6.0
  • PCI Express 6.0
  • PCIe FEC

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