Latest Posts

Aug 19, 2021

The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.

  • PCIe 6.0
  • PCI Express 6.0
  • PAM4
  • PCIe FEC
  • Forward Error Correction
  • FLIT
Apr 09, 2021

With global health and safety concerns related to the Covid-19 pandemic still greatly limiting in-person events in 2021, PCI-SIG® continues to offer compliance workshop opportunities to our members virtually.

  • Standards & Compliance
  • PCIe 6.0 specification
  • PAM4 signaling
  • PCIe 6.0 architecture
  • PCIe form factor
  • FLIT Mode
  • PCIe FEC
Apr 09, 2021

With global health and safety concerns related to the Covid-19 pandemic still greatly limiting in-person events in 2021, PCI-SIG® continues to offer compliance workshop opportunities to our members virtually.

  • Standards & Compliance
  • PCIe 6.0 specification
  • PAM4 signaling
  • PCIe 6.0 architecture
  • PCIe form factor
  • FLIT Mode
  • PCIe FEC
Sep 28, 2020

The PCI Express® (PCIe®) 6.0 specification will feature two primary mechanisms to correct errors: Forward Error Correction (FEC) and Cyclic Redundancy Check (CRC). Each 256-byte FLIT comprises of 242 bytes of payload which are protected by 8 Bytes of CRC.

  • Systems & Applications
  • PCIe 6.0
  • PCI Express 6.0
  • PCIe FEC
Aug 11, 2020

One of the many new features included in the PCI Express® (PCIe®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.

  • Systems & Applications
  • PCIe 6.0
  • PCI Express 6.0
  • What is PAM4
  • PAM4
  • PCIe FEC
  • Forward Error Correction
Jun 22, 2020

For almost two decades, the PCI Express® (PCIe®) architecture has offered low latency and high bandwidth in support of next generation systems.

  • Systems & Applications
  • PCIe 6.0
  • PCI Express 6.0
  • PAM4
  • PCIe FEC
  • Forward Error Correction
  • FLIT
Feb 27, 2020

At this year’s Open Compute Project Global Summit in San Jose on March 4 -5, attendees will have the opportunity to learn how PCI Express® (PCIe®) specifications enable OCP systems today and how newer versions of

  • Systems & Applications
  • PCIe 6.0
  • PCI Express 6.0
  • PCIe 5.0
  • PCI Express 5.0
  • PCIe 4.0
  • PCI Express 4.0
  • OCP Summit
  • Open Compute Project
Feb 19, 2020

We are starting 2020 with the release of version 0.5 of the PCI Express® (PCIe®) 6.0 specification incorporating the significant member feedback received on version 0.3.

  • Standards & Compliance
  • PCIe 6.0
  • PCI Express 6.0
  • PAM4
  • PCIe FEC
  • Forward Error Correction
  • FLIT
  • PCI Express specification
Oct 14, 2019

I’m pleased to share that PCI-SIG® continues to make great progress on the development of our next generation of PCIe® technology – the 

  • Physical Form Factors
  • PCIe 6.0
  • PCI Express 6.0
  • PCIe PAM4
  • PCIe FEC
  • PCIe Forward Error Correction
  • PCIe 6.0 specification
  • PCI Express 6.0 Specification
Jun 19, 2019

I am happy to share that PCI-SIG® has begun developing the PCI Express® (PCIe®) 6.0 specification, targeted for release in 2021.

  • Systems & Applications
  • PCIe 6.0
  • PCI Express 6.0
  • PCIe PAM4
  • PCIe FEC
  • PCIe Forward Error Correction
  • PCIe 6.0 specification
  • PCI Express 6.0 Specification
  • PCI Express PAM4
  • PCIe 6.0 FEC
  • PCI Express 6.0 FEC
  • PCIe6.0 Forward Error Correction
  • PCI Express 6.0 Forward Error Correction
Apr 25, 2018

I recently attended the OCP Summit for the first time and I was impressed by the size of this growing event. The San Jose Convention Center was packed with industry experts – all eager to discuss how to move the Open Compute Project (OPC) forward.

  • Systems & Applications
  • PCI-SIG
  • OCP Summit
  • Open Compute Project
  • PCIe 4.0
  • PCI Express 4.0