Latest Posts

Oct 03, 2023

Servers are challenged to process more intricate and diverse types of workloads in cloud, hybrid-cloud and enterprise data centers.

  • Systems & Applications
  • AI
  • Data Centers
  • Servers
  • PCIe 5.0 specification
  • PCIe 6.0 specification
  • PCIe retimers
Jan 11, 2022

Infographic of the PCIe 6.0 Architecture

  • Standards & Compliance
  • PCIe 6.0
  • PCI Express 6.0
  • PAM4
  • PCIe Storage
  • PCI Express specification
  • FLIT
  • Forward Error Correction
Dec 18, 2021

PCI-SIG® has continued to host PCI Express® (PCIe®) Compliance Workshops throughout 2021 as we recognize that they are an important member benefit.

  • Standards & Compliance
  • Compliance
  • PCIe 5.0 specification
  • PCIe 5.0
  • PCI-SIG Integrators List
  • PCI Express 5.0
Dec 14, 2021

PCI-SIG® built upon our momentum from 2020 with another successful year in 2021. From progress on the PCIe 5.0 architecture compliance program to the impending release of the PCIe 6.0 specification, we have hit many exciting milestones.

  • Standards & Compliance
  • PCI Express 5.0
  • PCI Express 6.0
  • PCI Express 6.0 Specification
  • PCI Express compliance
  • PCI Express specification
  • PCI-SIG
  • PCI-SIG Compliance
  • PCI-SIG Membership
  • PCIe 5.0 specification
  • PCIe 6.0 specification
Aug 19, 2021

The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.

  • PCIe 6.0
  • PCI Express 6.0
  • PAM4
  • PCIe FEC
  • Forward Error Correction
  • FLIT
Jan 22, 2021

With the widespread adoption of compute-intensive workloads – such as artificial intelligence and machine learning – in enterprise and cloud data centers, high-speed, low-latency interconnects like PCI Express® architecture are required to connect high-performance nodes.

  • Standards & Compliance
  • PCIe 4.0
  • PCIe 5.0
  • PCIe retimers
  • PCIe redrivers
  • PCIe 5.0 specification
Aug 11, 2020

One of the many new features included in the PCI Express® (PCIe®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.

  • Systems & Applications
  • PCIe 6.0
  • PCI Express 6.0
  • What is PAM4
  • PAM4
  • PCIe FEC
  • Forward Error Correction
Jun 23, 2020

PCI-SIG® has shifted to virtual events for the 2020 calendar year and our first major members event was the Virtual PCI-SIG Developers Conference.

  • Systems & Applications
  • PCI-SIG DevCon
  • PCIe 5.0
  • PCI Express 5.0
  • PCIe 4.0
  • PCI Express 4.0 PCIe Retimer
  • PCI Express Retimer
Jun 22, 2020

For almost two decades, the PCI Express® (PCIe®) architecture has offered low latency and high bandwidth in support of next generation systems.

  • Systems & Applications
  • PCIe 6.0
  • PCI Express 6.0
  • PAM4
  • PCIe FEC
  • Forward Error Correction
  • FLIT
Feb 19, 2020

We are starting 2020 with the release of version 0.5 of the PCI Express® (PCIe®) 6.0 specification incorporating the significant member feedback received on version 0.3.

  • Standards & Compliance
  • PCIe 6.0
  • PCI Express 6.0
  • PAM4
  • PCIe FEC
  • Forward Error Correction
  • FLIT
  • PCI Express specification
Jul 23, 2019

The SD Association (SDA) recently announced SD Express, which adds the PCI Express® and NVMe™ interfaces to the SD interface. The PCIe® interface delivers transfer rates up to 985 megabytes per second (MB/s) and supports backward compatibility with existing SD hosts.

  • Standards & Compliance
  • PCI-SIG
  • SD Association
  • SD Express
  • NVMe
  • PCIe 3.0
  • PCI Express 3.0
Feb 06, 2019

This is already shaping up to be a busy year for PCI-SIG® with the pending release of the PCI Express® 5.0 specification targete

  • Standards & Compliance
  • PCIe 5.0
  • PCI Express 5.0
  • Embedded World
  • SD Association
  • OCP Global Summit