Latest Posts

Jan 11, 2022

Infographic of the PCIe 6.0 Architecture

  • Standards & Compliance
  • PCIe 6.0
  • PCI Express 6.0
  • PAM4
  • PCIe Storage
  • PCI Express specification
  • FLIT
  • Forward Error Correction
Aug 19, 2021

The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.

  • PCIe 6.0
  • PCI Express 6.0
  • PAM4
  • PCIe FEC
  • Forward Error Correction
  • FLIT
Aug 30, 2020

The upcoming PCI Express® (PCIe®) 6.0 specification will continue PCI-SIG’s® longstanding history of innovation for the next generation of products to keep up with evolving needs in a wide range of markets.

  • Systems & Applications
  • PCIe 6.0
  • PCI Express 6.0
  • PCIe L0p
  • PCIe low power state
Aug 11, 2020

One of the many new features included in the PCI Express® (PCIe®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.

  • Systems & Applications
  • PCIe 6.0
  • PCI Express 6.0
  • What is PAM4
  • PAM4
  • PCIe FEC
  • Forward Error Correction
Jun 22, 2020

For almost two decades, the PCI Express® (PCIe®) architecture has offered low latency and high bandwidth in support of next generation systems.

  • Systems & Applications
  • PCIe 6.0
  • PCI Express 6.0
  • PAM4
  • PCIe FEC
  • Forward Error Correction
  • FLIT
Feb 19, 2020

We are starting 2020 with the release of version 0.5 of the PCI Express® (PCIe®) 6.0 specification incorporating the significant member feedback received on version 0.3.

  • Standards & Compliance
  • PCIe 6.0
  • PCI Express 6.0
  • PAM4
  • PCIe FEC
  • Forward Error Correction
  • FLIT
  • PCI Express specification
Jul 31, 2018

I’m looking forward to attending the Flash Memory Summit (FMS) next week in Santa Clara.

  • Standards & Compliance
  • PCI-SIG
  • Flash Memory Summit
  • FMS
  • NVMe
  • Flash Storage