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As the complexity of computer workloads in the automotive market increase, so does the sophistication of computers in vehicles, along with the interconnect performance requirements. A unique emerging challenge is Automotive Functional Safety (FuSA).
- Systems & Applications
- automotive
- PCI Express
- PCIe Specification
- PCIe 5.0
- PCIe 6.0
Servers are challenged to process more intricate and diverse types of workloads in cloud, hybrid-cloud and enterprise data centers.
- Systems & Applications
- AI
- Data Centers
- Servers
- PCIe 5.0 specification
- PCIe 6.0 specification
- PCIe retimers
It’s hard to believe it’s been 30 years since PCI-SIG® formed in 1992.
- Standards & Compliance
- Compliance
- PCI Express 5.0
- PCIe 5.0 Compliance
- PCI-SIG
- PCI-SIG Compliance
- PCI-SIG Integrators List
Infographic of the PCIe 6.0 Architecture
- Standards & Compliance
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe Storage
- PCI Express specification
- FLIT
- Forward Error Correction
PCI-SIG® Compliance Workshop Updates: Workshop #118 Recap, PCIe 5.0 Specification Workshops and More
PCI-SIG® has continued to host PCI Express® (PCIe®) Compliance Workshops throughout 2021 as we recognize that they are an important member benefit.
- Standards & Compliance
- Compliance
- PCIe 5.0 specification
- PCIe 5.0
- PCI-SIG Integrators List
- PCI Express 5.0
PCI-SIG® Compliance Workshop Updates: Workshop #118 Recap, PCIe 5.0 Specification Workshops and More
PCI-SIG® has continued to host PCI Express® (PCIe®) Compliance Workshops throughout 2021 as we recognize that they are an important member benefit.
- Standards & Compliance
- Compliance
- PCIe 5.0 specification
- PCIe 5.0
- PCI-SIG Integrators List
- PCI Express 5.0
The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe FEC
- Forward Error Correction
- FLIT
With the widespread adoption of compute-intensive workloads – such as artificial intelligence and machine learning – in enterprise and cloud data centers, high-speed, low-latency interconnects like PCI Express® architecture are required to connect high-performance nodes.
- Standards & Compliance
- PCIe 4.0
- PCIe 5.0
- PCIe retimers
- PCIe redrivers
- PCIe 5.0 specification
With the widespread adoption of compute-intensive workloads – such as artificial intelligence and machine learning – in enterprise and cloud data centers, high-speed, low-latency interconnects like PCI Express® architecture are required to connect high-performance nodes.
- Standards & Compliance
- PCIe 4.0
- PCIe 5.0
- PCIe retimers
- PCIe redrivers
- PCIe 5.0 specification
One of the many new features included in the PCI Express® (PCIe®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.
- Systems & Applications
- PCIe 6.0
- PCI Express 6.0
- What is PAM4
- PAM4
- PCIe FEC
- Forward Error Correction