Infographic of the PCIe 6.0 Architecture

Wow, 2020 sure has transformed the ways we connect, learn and innovate in industries around the world, and in our daily lives!

PCI Express^® (PCIe^®) technology is the most important high-speed serial bus in servers. Due to its high bandwidth and low latency characteristics, PCI Express architecture is widely used in various server interconnect scenarios, such as:

We are starting 2020 with the release of version 0.5 of the PCI Express^® (PCIe^®) 6.0 specification incorporating the significant member feedback received on version 0.3.

From Israel to Europe and Japan to Taiwan, the PCI-SIG^® Israel, Europe and APAC 2019 Developers Conference tour has come to an end for the year.

Earlier this month, I attended another eventful Flash Memory Summit (FMS) and I am pleased to say that PCI Express^® (PCIe^®) was around every corner at this year’s event.

This year’s Flash Memory Summit (FMS) is coming up on August 6. As PCI Express technologies continue to evolve and make strides in the industry, PCI-SIG^® is excited to highlight our participation in the growth of flash storage.

The SD Association (SDA) recently announced SD Express, which adds the PCI Express^® and NVMe™ interfaces to the SD interface. The PCIe^® interface delivers transfer rates up to 985 megabytes per second (MB/s) and supports backward compatibility with existing SD hosts.

The SD Association (SDA) recently announced SD Express, which adds the PCI Express^® and NVMe™ interfaces to the SD interface. The PCIe^® interface delivers transfer rates up to 985 megabytes per second (MB/s) and supports backward compatibility with existing SD hosts.

At PCI-SIG, we take pride in ensuring that our specifications operate without a hitch. However, sometimes PCI Express developers need to submit Engineering Change Requests (ECRs) to update parts of the specification so that PCIe integrated products can reach their optimal functionality.

At PCI-SIG, we take pride in ensuring that our specifications operate without a hitch. However, sometimes PCI Express developers need to submit Engineering Change Requests (ECRs) to update parts of the specification so that PCIe integrated products can reach their optimal functionality.

I’m happy to share that 2018 has been another productive year for PCI-SIG. In addition to significant progress in our specification development and compliance work, we also continued to provide educational resources to our members and the industry.

I’m looking forward to attending the Flash Memory Summit (FMS) next week in Santa Clara.