By Scott Knowlton and Mihaela Erler, PCI-SIG MWG Co-Chairs

The PCI-SIG® Board of Directors honored three individuals for their years of service and contributions to the development and expansion of PCI Express® (PCIe®) technology during the PCI-SIG US DevCon 2022 on June 21-22 in

It’s hard to believe it’s been 30 years since PCI-SIG® formed in 1992.

PCI-SIG® built upon our momentum from 2020 with another successful year in 2021. From progress on the PCIe 5.0 architecture compliance program to the impending release of the PCIe 6.0 specification, we have hit many exciting milestones.

The CXL™ Consortium and PCI-SIG® are excited to announce a memorandum of understanding (MOU) between the two organizations.

With the widespread adoption of compute-intensive workloads – such as artificial intelligence and machine learning – in enterprise and cloud data centers, high-speed, low-latency interconnects like PCI Express^® architecture are required to connect high-performance nodes.

Despite the many challenges in 2020, we are proud to report that it has been a successful year for, PCI-SIG^®.  We continued the momentum started in 2019 with PCIe^® 4.0 Compliance Testing, continued work on the PCIe 6.0 specification, and brought our members new ways to engag

Wow, 2020 sure has transformed the ways we connect, learn and innovate in industries around the world, and in our daily lives!

Our PCI-SIG^® members have been hard at work. In 2017, we delivered PCI Express^® 4.0 with its 16 GT/s, while also diving headfirst into PCI Express 5.0 development – first announced at our annual PCI-SIG DevCon in June 2017.

Earlier this month, I attended another eventful Flash Memory Summit (FMS) and I am pleased to say that PCI Express^® (PCIe^®) was around every corner at this year’s event.

This year’s Flash Memory Summit (FMS) is coming up on August 6. As PCI Express technologies continue to evolve and make strides in the industry, PCI-SIG^® is excited to highlight our participation in the growth of flash storage.

This year’s Flash Memory Summit (FMS) is coming up on August 6. As PCI Express technologies continue to evolve and make strides in the industry, PCI-SIG^® is excited to highlight our participation in the growth of flash storage.

The SD Association (SDA) recently announced SD Express, which adds the PCI Express^® and NVMe™ interfaces to the SD interface. The PCIe^® interface delivers transfer rates up to 985 megabytes per second (MB/s) and supports backward compatibility with existing SD hosts.

The SD Association (SDA) recently announced SD Express, which adds the PCI Express^® and NVMe™ interfaces to the SD interface. The PCIe^® interface delivers transfer rates up to 985 megabytes per second (MB/s) and supports backward compatibility with existing SD hosts.

Another PCI-SIG Developers Conference has come and gone, and we had a whopping 600+ member company attendees at this year’s event in Santa Clara.

This June 18-19, PCI-SIG and its 800+ member companies return to the Santa Clara Convention Center for the largest member event of the year: the Annual Members Meeting and Developers Conference.

PCI-SIG^® is proud to announce that we have established a working relationship with DMTF to simplify hardware management.

PCI-SIG^® is proud to announce that we have established a working relationship with DMTF to simplify hardware management.

This June 18-19, PCI-SIG and its 800+ member companies return to the Santa Clara Convention Center for the largest member event of the year: the Annual Members Meeting and Developers Conference.

At PCI-SIG, we take pride in ensuring that our specifications operate without a hitch. However, sometimes PCI Express developers need to submit Engineering Change Requests (ECRs) to update parts of the specification so that PCIe integrated products can reach their optimal functionality.

This is already shaping up to be a busy year for PCI-SIG^® with the pending release of the PCI Express^® 5.0 specification targete

I’m happy to share that 2018 has been another productive year for PCI-SIG. In addition to significant progress in our specification development and compliance work, we also continued to provide educational resources to our members and the industry.

Our PCI-SIG^® members have been hard at work. In 2017, we delivered PCI Express^® 4.0 with its 16 GT/s, while also diving headfirst into PCI Express 5.0 development – first announced at our annual PCI-SIG DevCon in June 2017.

The PCI-SIG Serial Enabling Workgroup (called the “SEG” for short) is the PCI-SIG workgroup charged with running the PCI Express^® (PCIe^®) compliance program.

By now, you probably know about the PCI-SIG Developers Conference which we hold in Santa Clara each year – a free event for our 750+ member companies with four tracks of presentations over two days.

I’m looking forward to attending the Flash Memory Summit (FMS) next week in Santa Clara.

Whew, what a week! That’s another PCI-SIG Developers Conference in the books though.

Whew, what a week! That’s another PCI-SIG Developers Conference in the books though.

After successfully releasing PCIe^® 4.0 Specification Version 1.0 last October, the members of the PCI-SIG^® have been heads down and hard at work to ensure PCIe 5.0 specification is made a reality by 2019.

Press conference on June 5 to announce PCIe 5.0 spec updates

I’m pleased to share that PCI-SIG has released the PCIe 4.0 Specification Version 1.0 and it is now available for download on our website.

I’m pleased to share that PCI-SIG has released the PCIe 4.0 Specification Version 1.0 and it is now available for download on our website.