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In 2022, PCI-SIG® introduced PCI Express® (PCIe®) 5.0 Compliance Testing to members. PCIe 5.0 specification official testing includes a maximum link speed of 32 GT/s.
- Standards and Compliance
- PCI Express 5.0
- PCI Express compliance
- PCIe 5.0 Compliance
- PCI-SIG Compliance
It’s hard to believe it’s been 30 years since PCI-SIG® formed in 1992.
- Standards & Compliance
- Compliance
- PCI Express 5.0
- PCIe 5.0 Compliance
- PCI-SIG
- PCI-SIG Compliance
- PCI-SIG Integrators List
With the ever-growing importance of security, we continue to see strong industry interest in Integrity and Data Encryption (IDE). As with any new technology, questions have been raised and addressed through new errata.
- Systems & Compliance
- PCIe Cybersecurity
- Integrity and Data Encryption (IDE)
- IO Security
Infographic of the PCIe 6.0 Architecture
- Standards & Compliance
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe Storage
- PCI Express specification
- FLIT
- Forward Error Correction
PCI-SIG® Compliance Workshop Updates: Workshop #118 Recap, PCIe 5.0 Specification Workshops and More
PCI-SIG® has continued to host PCI Express® (PCIe®) Compliance Workshops throughout 2021 as we recognize that they are an important member benefit.
- Standards & Compliance
- Compliance
- PCIe 5.0 specification
- PCIe 5.0
- PCI-SIG Integrators List
- PCI Express 5.0
PCI-SIG® built upon our momentum from 2020 with another successful year in 2021. From progress on the PCIe 5.0 architecture compliance program to the impending release of the PCIe 6.0 specification, we have hit many exciting milestones.
- Standards & Compliance
- PCI Express 5.0
- PCI Express 6.0
- PCI Express 6.0 Specification
- PCI Express compliance
- PCI Express specification
- PCI-SIG
- PCI-SIG Compliance
- PCI-SIG Membership
- PCIe 5.0 specification
- PCIe 6.0 specification
The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe FEC
- Forward Error Correction
- FLIT
One of the many new features included in the PCI Express® (PCIe®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.
- Systems & Applications
- PCIe 6.0
- PCI Express 6.0
- What is PAM4
- PAM4
- PCIe FEC
- Forward Error Correction
PCI-SIG® has shifted to virtual events for the 2020 calendar year and our first major members event was the Virtual PCI-SIG Developers Conference.
- Systems & Applications
- PCI-SIG DevCon
- PCIe 5.0
- PCI Express 5.0
- PCIe 4.0
- PCI Express 4.0 PCIe Retimer
- PCI Express Retimer
For almost two decades, the PCI Express® (PCIe®) architecture has offered low latency and high bandwidth in support of next generation systems.
- Systems & Applications
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe FEC
- Forward Error Correction
- FLIT