Latest Posts
Infographic of the PCIe 6.0 Architecture
- Standards & Compliance
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe Storage
- PCI Express specification
- FLIT
- Forward Error Correction
With the widespread adoption of compute-intensive workloads – such as artificial intelligence and machine learning – in enterprise and cloud data centers, high-speed, low-latency interconnects like PCI Express® architecture are required to connect high-performance nodes.
- Standards & Compliance
- PCIe 4.0
- PCIe 5.0
- PCIe retimers
- PCIe redrivers
- PCIe 5.0 specification
We are starting 2020 with the release of version 0.5 of the PCI Express® (PCIe®) 6.0 specification incorporating the significant member feedback received on version 0.3.
- Standards & Compliance
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe FEC
- Forward Error Correction
- FLIT
- PCI Express specification
The SD Association (SDA) recently announced SD Express, which adds the PCI Express® and NVMe™ interfaces to the SD interface. The PCIe® interface delivers transfer rates up to 985 megabytes per second (MB/s) and supports backward compatibility with existing SD hosts.
- Standards & Compliance
- PCI-SIG
- SD Association
- SD Express
- NVMe
- PCIe 3.0
- PCI Express 3.0
On January 22, 2019, the U.S. Cybersecurity and Infrastructure Security Agency issued an emergency directive to mitigate DNS infrastructure tampering intended to disrupt and redirect government and business communications.
- Standards & Compliance
- PCIe Cybersecurity
- Secure Boot
- PCIe Component Authentication
- Firmware
I’m looking forward to attending the Flash Memory Summit (FMS) next week in Santa Clara.
- Standards & Compliance
- PCI-SIG
- Flash Memory Summit
- FMS
- NVMe
- Flash Storage
Press conference on June 5 to announce PCIe 5.0 spec updates
- Standards & Compliance
- PCI Express 5.0
- PCI-SIG
- PCIe 5.0
- Developers Conference
- Specification