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I am excited to report that PCI-SIG has released PCIe 6.0 specification, version 0.9 to our members. This is a major milestone in our continued effort to double the data rate of the PCI Express® specifications while maintaining backwards compatibility.
- Standards & Compliance
- PCIe 6.0 specification
- PCIe 6.0
- PAM4
- PCIe FEC
- FLIT
- PCI Express specification
The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe FEC
- Forward Error Correction
- FLIT
With global health and safety concerns related to the Covid-19 pandemic still greatly limiting in-person events in 2021, PCI-SIG® continues to offer compliance workshop opportunities to our members virtually.
- Standards & Compliance
- PCIe 6.0 specification
- PAM4 signaling
- PCIe 6.0 architecture
- PCIe form factor
- FLIT Mode
- PCIe FEC
With the widespread adoption of compute-intensive workloads – such as artificial intelligence and machine learning – in enterprise and cloud data centers, high-speed, low-latency interconnects like PCI Express® architecture are required to connect high-performance nodes.
- Standards & Compliance
- PCIe 4.0
- PCIe 5.0
- PCIe retimers
- PCIe redrivers
- PCIe 5.0 specification
Despite the many challenges in 2020, we are proud to report that it has been a successful year for, PCI-SIG®. We continued the momentum started in 2019 with PCIe® 4.0 Compliance Testing, continued work on the PCIe 6.0 specification, and brought our members new ways to engag
- Standards & Compliance
- PCIe 6.0 specification
- PCIe 4.0
- PCI-SIG DevCon
Wow, 2020 sure has transformed the ways we connect, learn and innovate in industries around the world, and in our daily lives!
- Standards & Compliance
- PCI Express compliance
- PCI-SIG Integrators List
- PCIe 4.0
- PCIe 3.0
The PCI Express® (PCIe®) 6.0 specification will feature two primary mechanisms to correct errors: Forward Error Correction (FEC) and Cyclic Redundancy Check (CRC). Each 256-byte FLIT comprises of 242 bytes of payload which are protected by 8 Bytes of CRC.
- Systems & Applications
- PCIe 6.0
- PCI Express 6.0
- PCIe FEC
One of the many new features included in the PCI Express® (PCIe®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.
- Systems & Applications
- PCIe 6.0
- PCI Express 6.0
- What is PAM4
- PAM4
- PCIe FEC
- Forward Error Correction
PCI-SIG® has shifted to virtual events for the 2020 calendar year and our first major members event was the Virtual PCI-SIG Developers Conference.
- Systems & Applications
- PCI-SIG DevCon
- PCIe 5.0
- PCI Express 5.0
- PCIe 4.0
- PCI Express 4.0 PCIe Retimer
- PCI Express Retimer
For almost two decades, the PCI Express® (PCIe®) architecture has offered low latency and high bandwidth in support of next generation systems.
- Systems & Applications
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe FEC
- Forward Error Correction
- FLIT
At this year’s Open Compute Project Global Summit in San Jose on March 4 -5, attendees will have the opportunity to learn how PCI Express® (PCIe®) specifications enable OCP systems today and how newer versions of
- Systems & Applications
- PCIe 6.0
- PCI Express 6.0
- PCIe 5.0
- PCI Express 5.0
- PCIe 4.0
- PCI Express 4.0
- OCP Summit
- Open Compute Project
We are starting 2020 with the release of version 0.5 of the PCI Express® (PCIe®) 6.0 specification incorporating the significant member feedback received on version 0.3.
- Standards & Compliance
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe FEC
- Forward Error Correction
- FLIT
- PCI Express specification
- Physical Form Factors
- PCIe 6.0
- PCI Express 6.0
- PCIe PAM4
- PCIe FEC
- PCIe Forward Error Correction
- PCIe 6.0 specification
- PCI Express 6.0 Specification
Retimers and redrivers have enabled longer physical channels in servers and storage systems since Peripheral Component Interface Express (PCIe®) 3.0 specification was first introduced almost 10 years ago.
- Signal Integrity
- PCIe 5.0
- PCI Express 5.0
- PCIe 4.0
- PCI Express 4.0
- PCIe Retimer
- PCIe Redriver
- PCI Express specification
Earlier this month, I attended another eventful Flash Memory Summit (FMS) and I am pleased to say that PCI Express® (PCIe®) was around every corner at this year’s event.
- Standards & Compliance
- PCIe 6.0
- PCI Express 6.0
- PCIe 5.0
- PCI Express 5.0
- PCIe 4.0
- PCI Express 4.0
- OCP Summit
- Flash Memory Summit
- PCIe Storage
- PCI Express Storage
This year’s Flash Memory Summit (FMS) is coming up on August 6. As PCI Express technologies continue to evolve and make strides in the industry, PCI-SIG® is excited to highlight our participation in the growth of flash storage.
- Standards & Compliance
- PCI-SIG
- PCIe 6.0
- PCI Express 6.0
- PCIe 5.0
- PCI Express 5.0
- PCIe 4.0
- PCI Express 4.0
- OCP Summit
- Flash Memory Summit
- PCIe Storage
- PCI Express Storage
I am happy to share that PCI-SIG® has begun developing the PCI Express® (PCIe®) 6.0 specification, targeted for release in 2021.
- Systems & Applications
- PCIe 6.0
- PCI Express 6.0
- PCIe PAM4
- PCIe FEC
- PCIe Forward Error Correction
- PCIe 6.0 specification
- PCI Express 6.0 Specification
- PCI Express PAM4
- PCIe 6.0 FEC
- PCI Express 6.0 FEC
- PCIe6.0 Forward Error Correction
- PCI Express 6.0 Forward Error Correction
PCI-SIG® is proud to announce that we have established a working relationship with DMTF to simplify hardware management.
- Standards & Compliance
- PCIe
- PCI Express
- PCI-SIG
- DMTF
- Redfish
- PCIe Security
This June 18-19, PCI-SIG and its 800+ member companies return to the Santa Clara Convention Center for the largest member event of the year: the Annual Members Meeting and Developers Conference.
- Standards & Compliance
- PCI-SIG
- PCI Express 5.0
- PCI Express 4.0
- PCIe 5.0
- PCIe 4.0
PCI-SIG has built its reputation on delivering high quality PCI Express® (PCIe) specifications that have doubled bandwidth on average every three years, while maintaining full backwards compatibility with prior generations.
- Signal Integrity
- PCIe Lane Margining
- PCIe 4.0
- PCI Express 4.0
- PCIe Bandwidth
- PCIe retimers
- PCIe Test Equipment
his year, I was lucky enough to be able to attend and present at the Open Compute Project Summit and though it has come and gone by now, I’m already looking forward to the next one!
- Systems & Applications
- PCI-SIG
- PCIe 4.0
- PCI Express 4.0
- Open Compute Project Summit
- PCIe 5.0
- PCI Express 5.0
Whew, what a week! That’s another PCI-SIG Developers Conference in the books though.
- Standards & Compliance
- PCI-SIG
- PCI Express 4.0
- PCIe 4.0
- PCI Express 5.0
- PCIe 5.0
I recently attended the OCP Summit for the first time and I was impressed by the size of this growing event. The San Jose Convention Center was packed with industry experts – all eager to discuss how to move the Open Compute Project (OPC) forward.
- Systems & Applications
- PCI-SIG
- OCP Summit
- Open Compute Project
- PCIe 4.0
- PCI Express 4.0
I’m pleased to share that PCI-SIG has released the PCIe 4.0 Specification Version 1.0 and it is now available for download on our website.
- Standards & Compliance
- PCIe 5.0
- PCI Express 5.0
- PCI Expres 4.0
- PCIe 4.0
- PCI-SIG