PCI-SIG^® in 2022: A Year to Celebrate

By Mihaela Erler and Scott Knowlton, PCI-SIG MWG Co-Chairs

Advanced IP Design for PCI Express® Technology

By Scott Knowlton, PCI-SIG MWG Co-Chair

With the ever-growing importance of security, we continue to see strong industry interest in Integrity and Data Encryption (IDE). As with any new technology, questions have been raised and addressed through new errata.

Introduction

For nearly three decades, PCI Express® (PCIe®) technology has served as the de facto high bandwidth, low latency interconnect. As the industry evolves to meet the needs of data-intensive applications, the PCIe specification has kept pace, enabling future innovation.

We are pleased to commence 2022 on a high note with the official release of the PCI Express® (PCIe®) 6.0 specification to members.

Infographic of the PCIe 6.0 Architecture

Infographic of the PCIe 6.0 Architecture

The CXL™ Consortium and PCI-SIG® are excited to announce a memorandum of understanding (MOU) between the two organizations.

With the emergence of autonomous vehicles, AI-based advanced driver assistance systems (ADAS) and in-vehicle infotainment (IVI), today’s automobiles are becoming high-tech “servers on wheels.” PCI Express® (PCIe®) technology is expanding to become the interconnect of choice in automotive applicat

With the emergence of autonomous vehicles, AI-based advanced driver assistance systems (ADAS) and in-vehicle infotainment (IVI), today’s automobiles are becoming high-tech “servers on wheels.” PCI Express® (PCIe®) technology is expanding to become the interconnect of choice in automotive applicat

The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.

By: Hope Bovenzi, Strategic Marketing, Astera Labs

By: Hope Bovenzi, Strategic Marketing, Astera Labs

The upcoming PCI Express^® (PCIe^®) 6.0 specification will continue PCI-SIG’s^® longstanding history of innovation for the next generation of products to keep up with evolving needs in a wide range of markets.

One of the many new features included in the PCI Express^® (PCIe^®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.

For almost two decades, the PCI Express^® (PCIe^®) architecture has offered low latency and high bandwidth in support of next generation systems.

At this year’s Open Compute Project Global Summit in San Jose on March 4 -5, attendees will have the opportunity to learn how PCI Express^® (PCIe^®) specifications enable OCP systems today and how newer versions of

We are starting 2020 with the release of version 0.5 of the PCI Express^® (PCIe^®) 6.0 specification incorporating the significant member feedback received on version 0.3.

The Internet of Things (IoT) Industry is rapidly growing in popularity and breadth of applications.

As I look back on 2019, I’m proud to report that it has been a banner year for PCI-SIG^®.

From Israel to Europe and Japan to Taiwan, the PCI-SIG^® Israel, Europe and APAC 2019 Developers Conference tour has come to an end for the year.

PCI Express^® (PCIe^®) technology is deployed worldwide by PCI-SIG member companies, so it only makes sense that PCI-SIG^® travels around the globe too.

PCI Express^® (PCIe^®) technology is deployed worldwide by PCI-SIG member companies, so it only makes sense that PCI-SIG^® travels around the globe too.

Earlier this month, I attended another eventful Flash Memory Summit (FMS) and I am pleased to say that PCI Express^® (PCIe^®) was around every corner at this year’s event.

Earlier this month, I attended another eventful Flash Memory Summit (FMS) and I am pleased to say that PCI Express^® (PCIe^®) was around every corner at this year’s event.

This year’s Flash Memory Summit (FMS) is coming up on August 6. As PCI Express technologies continue to evolve and make strides in the industry, PCI-SIG^® is excited to highlight our participation in the growth of flash storage.

This year’s Flash Memory Summit (FMS) is coming up on August 6. As PCI Express technologies continue to evolve and make strides in the industry, PCI-SIG^® is excited to highlight our participation in the growth of flash storage.

The SD Association (SDA) recently announced SD Express, which adds the PCI Express^® and NVMe™ interfaces to the SD interface. The PCIe^® interface delivers transfer rates up to 985 megabytes per second (MB/s) and supports backward compatibility with existing SD hosts.

PCI-SIG^® is proud to announce that we have established a working relationship with DMTF to simplify hardware management.

PCI-SIG^® is proud to announce that we have established a working relationship with DMTF to simplify hardware management.

PCI-SIG has built its reputation on delivering high quality PCI Express^® (PCIe) specifications that have doubled bandwidth on average every three years, while maintaining full backwards compatibility with prior generations.

I’m happy to share that 2018 has been another productive year for PCI-SIG. In addition to significant progress in our specification development and compliance work, we also continued to provide educational resources to our members and the industry.

PCI Express^® – also known as PCIe – used to get a bad rap for being power hungry on servers and PCs. But I’m happy to say that this is no longer the case. Are you aware that PCIe today is extremely power efficient with built-in low power features?

I’m looking forward to attending the Flash Memory Summit (FMS) next week in Santa Clara.

I recently attended the OCP Summit for the first time and I was impressed by the size of this growing event. The San Jose Convention Center was packed with industry experts – all eager to discuss how to move the Open Compute Project (OPC) forward.