Infographic of the PCIe 6.0 Architecture

With the emergence of autonomous vehicles, AI-based advanced driver assistance systems (ADAS) and in-vehicle infotainment (IVI), today’s automobiles are becoming high-tech “servers on wheels.” PCI Express® (PCIe®) technology is expanding to become the interconnect of choice in automotive applicat

The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.

By: Hope Bovenzi, Strategic Marketing, Astera Labs

The upcoming PCI Express^® (PCIe^®) 6.0 specification will continue PCI-SIG’s^® longstanding history of innovation for the next generation of products to keep up with evolving needs in a wide range of markets.

One of the many new features included in the PCI Express^® (PCIe^®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.

PCI-SIG^® has shifted to virtual events for the 2020 calendar year and our first major members event was the Virtual PCI-SIG Developers Conference.

For almost two decades, the PCI Express^® (PCIe^®) architecture has offered low latency and high bandwidth in support of next generation systems.

We are starting 2020 with the release of version 0.5 of the PCI Express^® (PCIe^®) 6.0 specification incorporating the significant member feedback received on version 0.3.

The first installment of the PCI-SIG^® educational webinar series, “Retimers to the Rescue: PCI Express^® Specifications Reach Their Full Potential” premiered on October 9, 2019.

Retimers and redrivers have enabled longer physical channels in servers and storage systems since Peripheral Component Interface Express (PCIe^®) 3.0 specification was first introduced almost 10 years ago.

I am happy to share that PCI-SIG^® has begun developing the PCI Express^® (PCIe^®) 6.0 specification, targeted for release in 2021.