Specifications

PCI-SIG specifications define standards driving the industry-wide compatibility of peripheral component interconnects. Members regularly review them, providing commentary and change requests when necessary. These requests are considered by technical workgroups and applied as appropriate, resulting in collaboratively devised specifications benefiting millions of platforms and add-in devices.

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Specifications Library

Technology: PCI Conventional
Specification Title Spec Rev Document Type Release Date
PCI Firmware Specification Revision 3.2
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer. show less
3.x Specification
Enhanced Allocation (EA) for Memory and I/O Resources
Enhanced Allocation is an optional Conventional PCI ...view more Enhanced Allocation is an optional Conventional PCI Capability that may be implemented by Functions to indicate fixed (non reprogrammable) I/O and memory ranges assigned to the Function, as well as supporting new resource “type” definitions and future extensibility to also support reprogrammable allocations. show less
3.x ECN
ACPI Additions for FW Latency Optimizations
This ECR provides two additional ACPI DSM functions ...view more This ECR provides two additional ACPI DSM functions to inform OS about the possible time reduction opportunities: show less
3.x ECN
PCIe Hot Plug
This ECN affects the PCI Firmware Specification v3.1...view more This ECN affects the PCI Firmware Specification v3.1 and allows certain errors to be suppressed by platform if software stack ensured error containment. Also removes the implementation note in section 4.5.2.4 which is not representative of OS behavior. show less
3.x ECN
UEFI Related Updates
Update the references to the latest UEFI Specificati...view more Update the references to the latest UEFI Specification. Make clarifications in 5.1.2 that the pointers to the Device List, the Configuration Utility Code header and the DMTF CLP Entry Point are not applicable to the UEFI Option ROMs. show less
3.x ECN
Changing Class Code for InfiniBand Adapter
This ECN updates the subclass ID description in the ...view more This ECN updates the subclass ID description in the Class Code & Capability ID Specification. show less
3.x ECN
PCI Firmware Specification Revision 3.1
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI™, PCI-X, and PCI Express® systems in a host computer. show less
3.x Specification
Class Code & Capability ID Extraction
This ECN extracts the Class Code definitions from Ap...view more This ECN extracts the Class Code definitions from Appendix D and the Capability ID definitions from Appendix H, for consolidation into a new standalone document that’s easier to maintain. The new document will also consolidate Extended Capability definitions from the PCIe Base spec and various other PCIe specs. show less
3.x ECN
PCIe Device Labeling under Operating Systems
This ECR proposes a mechanism (new extension to _DSM...view more This ECR proposes a mechanism (new extension to _DSM) to make the device names/labels under Operating Systems deterministic. Currently, there is no well defined mechanism to consistently associate platform specific device names and instances of a device type under operating system. As a result, instance labels for specific device types under various operating systems (ex: ethx label for networking device instance under Linux OS) do not always map into the platform designated device labels. Additionally, the instance labels can change based on the system configuration. For example, under Linux operating systems, the “eth0” label does not necessarily map to the first embedded networking device as designed in a given platform. Depending on the hardware bus topology, current configuration including the number and type of networking adapters installed, the eth0 label assignment could change in a given platform. show less
3.x ECN
ACPI Additions for ASPM, OBFF, LTR ECNs
A number of PCIe base specifications ECNs have been ...view more A number of PCIe base specifications ECNs have been approved that require software support. In some cases, platform firmware needs to know if the OS running supports certain features, or the OS needs to be able to request control of certain features from platform firmware. In other cases, the OS needs to know information about the platform that cannot be discovered through PCI enumeration, and ACPI must be used to supply the additional information. show less
3.x ECN
Update DMTF SM CLP Specification References
This update references to sections in the DMTF Serve...view more This update references to sections in the DMTF Server Management Command Line Protocol (SM CLP) Specification (DSP0214) to match the most recent version SM CLP Specification (v1.0.2). It also clarifies that the references to the DMTF SM CLP specification are referencing v1.0.2. and adds a reference to the DMTF SM CLP specification in section 1.2 Reference Documents. show less
3.x ECN
UEFI PCI Services Update
This is a request to update the UEFI PCI Services....view more This is a request to update the UEFI PCI Services. No functional changes. In the case of the UGA reference, UGA has been obsolete by the UEFI Specification and is replaced by the new GOP. show less
3.x ECN
Unoccupied Slot Power Hand-off State Clarification
This ECN allows the unoccupied slots' power to be of...view more This ECN allows the unoccupied slots' power to be off at hand-off, which is a reasonable implementation and many systems implement that way today. show less
3.x ECN
PCI Option ROM CLP
This ECN rectifies the differences between the DMTF ...view more This ECN rectifies the differences between the DMTF SM CLP Specification and its supporting documents with the current PCI Firmware 3.0 Specification. Also, it clarifies the supporting documents required for successfully implementing CLP in an X86 PCI FW 3.0 compatible option ROM. show less
3.x ECN
Errata for PCI 3.0 3.x Errata
Advanced Capabilities for Conventional PCI
For conventional PCI devices integrated into a PCI E...view more For conventional PCI devices integrated into a PCI Express Root Complex, this defines an optional capability structure that includes selected advanced features originally defined for PCI Express. This capability is intended to be extensible in the future. For the initial definition, the Transactions Pending (TP) and Function Level Reset (FLR) are included. show less
3.x ECN
PCI_OSC Clarifications
This ECN attempts to make clarifications such that t...view more This ECN attempts to make clarifications such that the system firmware and multiple operating systems can have the same interpretation of the specification and work interoperably. show less
3.x ECN
Ignore PCI Boot Configuration_DSM Function
This ECN adds a function to the _DSM Definitions for...view more This ECN adds a function to the _DSM Definitions for PCI to provide an indication to an operating system that it can ignore the PCI boot configuration setup by the firmware during system initialization. show less
3.x ECN
PCI Firmware Specification Revision 3.0
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer. show less
3.x Specification
Interrupt Line Register Usage
This ECN is a request for modifications to the parag...view more This ECN is a request for modifications to the paragraphs describing the Interrupt Line Register usage for the PCI-to-PCI-Bridge. The purpose is to clarify the differences between the usages on PC-compatible systems and DIG64-compliant systems. show less
1.x ECN
Generic Capability Structure for SATA Host Bus Adapters
The functional changes proposed involve the definiti...view more The functional changes proposed involve the definition of a new Capabilities List ID (and associated Capability register set). This new Capabilities ID will identify to system firmware (BIOS/OROM), a Serial ATA (SATA) host bus adapter’s (HBA) support of optional features that may be defined in the particular SATA HBA specification (i.e. Advanced Host Controller Interface - AHCI). show less
3.x ECN
PCI Bus Power Management Interface Specification Revision 1.2
The goal of this specification is to establish a sta...view more The goal of this specification is to establish a standard set of PCI peripheral power management hardware interfaces and behavioral policies. Once established, this infrastructure enables an operating system to intelligently manage the power of PCI functions and buses. show less
1.x Specification
PCI Local Bus Specification Revision 3.0
This document contains the formal specifications of ...view more This document contains the formal specifications of the protocol, electrical, and mechanical features of the PCI Local Bus Specification, Revision 3.0, as the production version effective February 3, 2004. The PCI Local Bus Specification, Revision 2.3, issued March 29, 2002, is not superseded by this specification. show less
3.x Specification
PCI Local Bus Specification Revision 3.0 with Change Bar
This document contains the formal specifications of ...view more This document contains the formal specifications of the protocol, electrical, and mechanical features of the PCI Local Bus Specification, Revision 3.0, as the production version effective February 3, 2004. The PCI Local Bus Specification, Revision 2.3, issued March 29, 2002, is not superseded by this specification. show less
3.x Specification
Errata for PCI 2.3 2.x Errata
SATA Class Code ECN
Create a new class code for SerialATA host-based ada...view more Create a new class code for SerialATA host-based adapters (HBAs) that can be identified by system software. The new class code will allow for system software to identify a controller as being attached to serial ATA devices and serial attached SCSI devices. This will help system software load drivers that may be specific to these interfaces. show less
3.x ECN
MSI-X
Extend the current MSI functionality to support a la...view more Extend the current MSI functionality to support a larger number of MSI vectors, plus a separate and independent Message Address and Message Data for each MSI vector. Allow more flexibility when SW allocates fewer MSI vectors than requested by HW. Enable per-vector masking capability. show less
2.x ECN
MSI-X
Extend the current MSI functionality to support a la...view more Extend the current MSI functionality to support a larger number of MSI vectors, plus a separate and independent Message Address and Message Data for each MSI vector. Allow more flexibility when SW allocates fewer MSI vectors than requested by HW. Enable per-vector masking capability. show less
3.x ECN
PCI-to-PCI Bridge Architecture Specification Revision 1.2
This specification defines the behavior of a complia...view more This specification defines the behavior of a compliant PCI-to-PCI bridge. A PCI-to-PCI bridge that conforms to this specification and the PCI Local Bus Specification is a compliant implementation. Compliant bridges may differ from each other in performance and, to some extent, functionality. show less
1.x Specification
PCI-to-PCI Bridge Architecture Specification Revision 1.2 with Change Bar
This specification defines the behavior of a complia...view more This specification defines the behavior of a compliant PCI-to-PCI bridge. A PCI-to-PCI bridge that conforms to this specification and the PCI Local Bus Specification is a compliant implementation. Compliant bridges may differ from each other in performance and, to some extent, functionality. show less
1.x Specification
SHPC Memory Access Granularity
Restrict PCI Standard Hot-Plug (SHPC) device drivers...view more Restrict PCI Standard Hot-Plug (SHPC) device drivers to a memory access granularity of maximum one DWORD (aligned) when reading or writing to the SHPC memory space. show less
1.x ECN
SHPC Extensions for PCI-X 2.0
Changes are to the PCI Standard Hot-Plug Controller ...view more Changes are to the PCI Standard Hot-Plug Controller and Subsystem Specification, Revision 1.0. This ECN extends the Standard Hot-plug Controller Specification to support the additional PCI-X speeds and modes allowed by the PCI-X 2.0 specification. Specifically, this ECN provides the required hardware and software extensions needed to support the new PCI-X 2.0 speeds of 266 and 533 and also the software extensions needed to control PCI-X 2.0 mode ECC and parity operation. show less
1.x ECN
PCI/PCI-X Connector Contact Finish Changes
The intent of this ECR is to update the PCI base spe...view more The intent of this ECR is to update the PCI base specifications to include PCI connector metallurgical practices which have been commonly accepted or introduced since the original wording was drafted before the PCI 2.0 specification. With an overwhelming majority of PCI and PCI-X connectors shipped in the world that do not meet the PCI specification for contact finish plating, the most efficient way to rectify the situation is to correct the specification. show less
2.x ECN
PCI/PCI-X Connector Contact Finish Changes
The intent of this ECR is to update the PCI base spe...view more The intent of this ECR is to update the PCI base specifications to include PCI connector metallurgical practices which have been commonly accepted or introduced since the original wording was drafted before the PCI 2.0 specification. With an overwhelming majority of PCI and PCI-X connectors shipped in the world that do not meet the PCI specification for contact finish plating, the most efficient way to rectify the situation is to correct the specification. show less
3.x ECN
PCI Local Bus Specification Revision 2.3
This document contains the formal specifications of ...view more This document contains the formal specifications of the protocol, electrical, and mechanical features of the PCI Local Bus Specification, Revision 2.3, as the production version effective March 29, 2002. The PCI Local Bus Specification, Revision 2.2, issued December 18, 1998, is superseded by this specification. show less
2.x Specification
PCI Hot-Plug Specification Revision 1.1
The primary objective of this specification is to en...view more The primary objective of this specification is to enable higher availability of file and application servers by standardizing key aspects of the process of removing and installing PCI add-in cards while the system is running. Although these same principles can be applied to desktop and portable systems using PCI buses, the operations described here target server platforms. show less
1.x Specification
PCI Standard Hot-Plug Controller and Subsystem Specification Revision 1.0
The primary purpose of this document is to specify a...view more The primary purpose of this document is to specify a standard implementation of a PCI Hot-Plug Controller called the Standard Hot-Plug Controller (SHPC). show less
1.x Specification
Mini PCI Specification Revision 1.0
The Mini PCI Specification defines an alternate impl...view more The Mini PCI Specification defines an alternate implementation for small form factor PCI cards referred to in this specification as a Mini PCI Card. This specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Local Bus Specification. show less
1.x Specification
PCI Bios Specification Revision 2.1
This document describes the software interface prese...view more This document describes the software interface presented by the PCI BIOS functions. This interface provides a hardware independent method of managing PCI devices in a host computer. show less
2.x Specification