PCI-X 2.0 is the next generation of PCI. It builds upon previous generations of PCI including the electricals, protocols, signals names and functions, connectors, etc. It also maintains backward compatibility with conventional PCI. It is the next logical advance in the world's most popular PC bus. There have been many generations of PCI, which all build upon each other. The PCI bus began with a 32-bit / 33MHz specification. Over time, to increase performance, 64-bit and 66MHz versions were introduced. To increase the bus speed and reduce latency PCI-X 1.0 was developed, with a maximum clock speed of 133 MHz. PCI-X 1.0 also introduced improved protocols, such as the split-transaction protocol which allows more efficient use of bus bandwidth, resulting in throughput gains beyond the simple increases in clock speed and bus width. Because of the demand for even higher throughput and to improve error correction, the PCI-X 2.0 specification was developed. It extends the bus frequency to 266 MHz and 533MHz and adds advanced features like Error Code Correction (ECC), while still maintaining backward compatibility to the first generation.