Frequently Asked Questions
The following FAQ list was generated using standard responses provided to PCI-SIG members by Technical Support and PCI-SIG Administration. For questions relative to the PCI Specifications, please reference the specifications themselves as the authoritative text.
PCI Express - 5.0
 Is the PCIe 5.0 architecture more expensive to implement than prior PCIe architectures? PCI-SIG attempts to define and evolve the PCIe architecture in a manner consistent with low-cost and high-volume manufacturability considerations. While PCI-SIG cannot comment on design choices and implementation costs, optimized silicon, die size, and power consumption continue to be important considerations that inform PCIe specification development and architecture evolution. |
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When was the PCIe 5.0 specification made available? PCI-SIG released the PCIe 5.0 specification on May 22, 2019. |
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What are the target applications for the PCIe 5.0 architecture? The PCIe 5.0 specification addresses the many applications pushing for increased bandwidth at a low cost, including server, workstation, desktop PC, notebook PC, tablets, embedded systems, peripheral devices, high-performance computing markets, and more. The target implementations are entirely at the discretion of the designer. |
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Why is a new generation of PCIe architecture needed? PCI-SIG responds to the needs of its members. As applications evolve to consume the I/O bandwidth provided by the current generation of the PCIe architecture, PCI-SIG begins to study the requirements for technology evolution to keep abreast of performance and feature requirements. |
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What are Retimers and when are they needed? Retimers were introduced with PCIe 4.0. Up to two Retimers are allowed between the Upstream Port and the Downstream Port of a Link. They are used when necessary to reliably extend the achievable channel length between two PCIe Ports. PCIe 4.0 and PCIe 5.0 Retimers are Physical Layer protocol aware. That is, they participate in Link Equalization, and they adjust their data rate of operation and their Link width in concert with the Upstream and Downstream Ports of the Link. |
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Are PCIe 5.0 products compatible with products built to prior PCIe generations? PCI-SIG is proud of its long heritage of developing compatible architectures and its members have consistently produced compatible and interoperable products. In keeping with this tradition, the PCIe 5.0 architecture is compatible with prior generations of this technology, from software to clocking architecture to mechanical interfaces. PCIe 1.x, 2.x, 3.x, and 4.x cards will seamlessly plug into PCIe 5.0-capable slots and operate at the highest performance levels possible. Similarly, all PCIe 5.0 cards will plug into PCIe 1.x-, PCIe 2.x-, PCIe 3.x- and PCIe 4.x-capable slots and operate at the highest performance levels supported by those configurations. |
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What bit rates does the PCIe 5.0 specification support and how does it compare to prior PCIe generations? A PCIe Link consists of 1, 2, 4, 8, 12, 16, or 32 Lanes, all operating at one of the supported signaling rates.
A PCIe 5.0 Link consisting of 32 Lanes and operating at a bit rate of 32 GT/s provides an effective raw bandwidth of 128 Gigabytes/second in each direction simultaneously. |
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Where can I find answers to questions about the PCIe 5.0 specifications that have been posted by other PCI-SIG members? Please see PCI-SIG Members Forum, which is a database of member-posted questions about PCIe specifications and the corresponding PCI-SIG answers. See also the Searching PCI-SIG Tech Forum document, which provides instructions on how to search for answers in the PCI-SIG Members Forum. |
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Will PCI-SIG host PCIe 5.0 Compliance Testing Workshops as it has for previous specification generations? Official Compliance Testing for PCIe 5.0 has been available since April 2022 and many PCIe 5.0 compliant systems, components, and add-in cards have already been added to the Integrators List. |
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What is PCI Express (PCIe) 5.0 and what requirements guided its development? The PCIe 5.0 architecture Is an evolution of the ubiquitous and general-purpose PCI Express I/O architecture. It supports a maximum bit rate that is double that of the PCIe 4.0 architecture. The key requirement for evolving the PCIe architecture is to continue to provide performance scaling consistent with bandwidth demand from a variety of applications, and with low cost, low power, and minimal perturbations at the platform level. One of the main factors in the wide adoption of the PCIe architecture is its sensitivity to high-volume manufacturing capabilities and materials, low-cost connectors and so on. |
PCI Express - 6.0
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What are the new features in the PCIe 6.0 specification? The PCIe 6.0 specification introduces PAM4 (Pulse Amplitude Modulation with 4 levels) signaling, low-latency Forward Error Correction (FEC) and Flit (Flow Control Unit)-based encoding. |
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How can I get a copy of the PCIe 6.0 specification? The final specification is available to all PCI-SIG members; join PCI-SIG to receive a copy. Members can download the specification here. |
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When do you anticipate products utilizing PCIe 6.0 technology will enter the market? The general timeline is 12-18 months after the release of the final specification. |
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Can Flit Mode and non-Flit Mode Links intercommunicate? Yes, automatic translation occurs at the boundaries |
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What is the bit rate for the PCIe 6.0 specification? How does it compare to previous generations of PCIe technology? The PCIe 6.0 specification supports a data rate of 64 GT/s and up to 256 GB/s via a x16 configuration, while providing low latency, minimal complexity and reduced bandwidth overhead. PCIe 6.0 technology delivers a doubling of the 32 GT/s and 128 GB/s bit rate of the PCIe 5.0 specification. |
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What is Forward Error Correction (FEC) and how is it utilized in the PCIe 6.0 specification? Lightweight Forward Error Correction (FEC) and strong Cyclic Redundancy Check (CRC) are the two primary methods used in the PCIe 6.0 specification to correct errors. With the 64 GT/s data rate enabled by PAM4 encoding in the PCIe 6.0 specification, the bit error rate (BER) was several orders of magnitude higher than the 10-12 BER in all prior generations. FEC and CRC mitigate the bit error rate and allow the PCIe 6.0 specification to reach new levels of performance. Flit Mode supports the higher BER expected in PAM4 (10-6 vs 10-12 in NRZ). This can provide increased resilience in NRZ environments. |
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What are the industry benefits of implementing PCIe 6.0 technology? PCIe 6.0 technology is cost-effective and scalable. By adopting PCIe 6.0 technology in their roadmaps, companies can future-proof their products and offer customers the high bandwidth and low latency technology they need. |
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What are the initial target applications for the PCIe 6.0 architecture? The initial target applications of PCIe 6.0 technology include servers, AI/ML, networking and storage in data-intensive markets like data center, HPC, industrial, automotive and Military/Aerospace. |
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Were bit tags adjusted in the PCIe 6.0 specification? Bit tags were increased to 14 bits to support a larger number of outstanding non-posted requests. We anticipate this wider size to work for at least the next generation as well. |
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Will there be a new compliance specification developed for the PCIe 6.0 specification? When will compliance testing begin? Yes, for each revision of the base specification, PCI-SIG develops compliance tests and related collateral consistent with the requirements of the new architecture. All of these compliance requirements are incremental in nature and build on the prior generation of the architecture. PCI-SIG anticipates releasing compliance specifications as they mature along with corresponding tests and measurement criteria. PCIe 6.0 Preliminary FYI testing is anticipated to begin in 2023. |
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Why is a new generation of PCIe architecture needed? Heterogeneous computing applications like artificial intelligence, machine learning and deep learning require a high-performance, low-latency I/O interconnect with additional performance over PCIe 5.0. |
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What is Flit Mode and why did PCI-SIG move to this unit of data exchange? Flit (Flow Control Unit) mode is the unit of data exchange in the PCIe 6.0 specification. PCI-SIG adopted a 256-Byte Flit structure, which includes the variable-sized Transaction Layer Packets (TLPs) and Data Link Layer Payloads (DLLPs). This is a necessary change due to the move to PAM4 encoding and Forward Error Correction (FEC), which only works on fixed-size data packets. Flit Mode is required for 64 GT/s PAM4 and is supported at all Link speeds. Once a Link trains to Flit Mode, it will stay in Flit Mode as long as that Link remains LinkUp. |
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What software changes were needed to take advantage of Flit Mode? A great deal of care has been taken to avoid significant impacts to existing software, but some changes could not be avoided in order to take full advantage of Flit mode. Here are some examples:
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Will PCIe 6.0 products be compatible with previous generations? Yes, PCIe 6.0 products will interoperate and maintain backwards compatibility with all previous generations of PCI Express technology. |
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What is the PCI Express (PCIe) 6.0 specification? The PCI Express 6.0 specification is the latest generation of PCIe technology, the ubiquitous and general-purpose PCI Express I/O specification. The PCIe 6.0 specification supports data-intensive markets like data centers, artificial intelligence/machine learning, HPC, automotive, IoT, and military aerospace. |
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Why does PCIe 6.0 specification utilize PAM4 signaling over NRZ signaling? PAM4 (Pulse Amplitude Modulation with 4 Levels) is a multilevel signal modulation format used to transmit data. NRZ uses two levels of signaling, while PAM4 uses four levels. It packs two bits of information into the same amount of time on a serial channel. The utilization of PAM4 allows the PCIe 6.0 specification to reach 64 GT/s data rate and up to 256 GB/s bidirectional bandwidth via a x16 configuration. |
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Does Flit Mode support error injection? Yes, Flit Mode supports an optional error injection mechanism. |
PCI Express - 7.0
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What markets will PCIe 7.0 specification address? PCIe 7.0 technology will expand the PCI-SIG roadmap to include data-intensive applications and markets, including 800 Gig Ethernet, Artificial Intelligence and Machine Learning (AI/ML), High Performance Computing (HPC), Quantum Computing, Hyperscale Data Centers and Cloud. |
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What are the feature goals for the PCIe 7.0 specification? PCI-SIG technical workgroups will be developing the PCIe 7.0 specification with the following feature goals:
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What is the expected data rate for the PCI-SIG 7.0 specification? The PCIe 7.0 specification is targeted to double the data rate of the PCIe 6.0 specification (64 GT/s) to 128 GT/s. |
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When will the PCIe 7.0 specification be finalized? The forthcoming PCIe 7.0 specification is planned for 2025. |
PCI Express - M-PHY
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Is there a need for new software to support the PCIe adaptation on the MIPI M-PHY? This adaptation of the PCIe architecture requires no new software. It reuses the existing, ubiquitous support in all major Operating Systems (e.g. pci.sys bus driver on Windows platforms). This includes existing support for device discovery, configuration and control. |
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What are the main applications of the PCIe adaptation on the MIPI M-PHY? The initial application of this technology is anticipated to be high-performance wireless communications with other applications based on device design requirements. Future implementations are expected in the handheld device market, including smartphones, tablets and other ultra-low power applications. As a power-efficient, general-purpose load-store I/O architecture, component and device designers can implement this technology in other I/O expansion usage models of their choosing as well. |
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What is the primary benefit of using PCIe architecture with the MIPI M-PHY? This collaboration will enable component and device manufacturers to take advantage of the reduction in I/O technology proliferation, allowing them to reduce their product development time, product validation time and significantly increase their time to market. The mobile and handset industry can realize these benefits today by adopting PCIe architecture adapted to run over M-PHY. |
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PCIe technology is in every server, workstation and laptop PC. Why is PCIe over M-PHY a suitable I/O technology for tablet and smartphone devices? As a broadly adopted technology standard, PCIe benefits from several decades of innovations with universal support in all major Operating Systems, a robust device discovery and configuration mechanism, and comprehensive power management capabilities that very few, if any, of the other I/O technologies can match. PCIe technology has a flexible, layered protocol that enables innovations to occur at each layer of the architecture independent of the other layers. In this way, power-efficient PHY technologies, such as MIPI M-PHY, can be integrated with the familiar and highly functional PCIe protocol stack to deliver best-in-class and highly scalable I/O performance in tablet and smartphone devices. |
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When and how will the PCI-SIG release the PCIe adaptation layer specification? The PCI-SIG will deliver this technology as an extension to the existing PCIe 3.0 Base specification via ECN by the end of 2012. This technology will be fully integrated into the next release of the PCIe Base specification, PCIe 4.0, enabling ease of access and reference. |
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Is there a name for the PCIe adaptation that operates with the MIPI M-PHY? The PCI-SIG has recently accepted this technology as a contribution from its members and will soon announce a suitable name for it. |
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Why is PCI-SIG adapting PCIe protocols to operate over the MIPI M-PHY specification? As PCs become lighter and thinner and tablets and smartphones become more functional, consumers want seamless, always on/always connected functionality from their computing devices. To respond to these market expectations, device manufacturers need efficient, intelligent I/O technologies. The PCIe architecture satisfies all of these requirements, and with the adaptation to operate over the M-PHY specification it can deliver consistent high performance in power-constrained platforms such as ULT laptops, tablets and smartphones. By delivering this technology, the PCI-SIG is meeting the emerging needs of its members and the industry. |
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