Frequently Asked Questions

The following FAQ list was generated using standard responses provided to PCI-SIG members by Technical Support and PCI-SIG Administration. For questions relative to the PCI Specifications, please reference the specifications themselves as the authoritative text. 

PCI Express - M-PHY

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Is there a name for the PCIe adaptation that operates with the MIPI M-PHY?

The PCI-SIG has recently accepted this technology as a contribution from its members and will soon announce a suitable name for it.
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Is there a need for new software to support the PCIe adaptation on the MIPI M-PHY?

This adaptation of the PCIe architecture requires no new software. It reuses the existing, ubiquitous support in all major Operating Systems (e.g. pci.sys bus driver on Windows platforms). This includes existing support for device discovery, configuration and control.
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Why is PCI-SIG adapting PCIe protocols to operate over the MIPI M-PHY specification?

As PCs become lighter and thinner and tablets and smartphones become more functional, consumers want seamless, always on/always connected functionality from their computing devices. To respond to these market expectations, device manufacturers need efficient, intelligent I/O technologies. The PCIe architecture satisfies all of these requirements, and with the adaptation to operate over the M-PHY specification it can deliver consistent high performance in power-constrained platforms such as ULT laptops, tablets and smartphones. By delivering this technology, the PCI-SIG is meeting the emerging needs of its members and the industry.
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What are the main applications of the PCIe adaptation on the MIPI M-PHY?

The initial application of this technology is anticipated to be high-performance wireless communications with other applications based on device design requirements. Future implementations are expected in the handheld device market, including smartphones, tablets and other ultra-low power applications. As a power-efficient, general-purpose load-store I/O architecture, component and device designers can implement this technology in other I/O expansion usage models of their choosing as well.

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