Frequently Asked Questions

The following FAQ list was generated using standard responses provided to PCI-SIG members by Technical Support and PCI-SIG Administration. For questions relative to the PCI Specifications, please reference the specifications themselves as the authoritative text. 

PCI Express - 3.0

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Does this mean that PCIe is finished at 8GT/s? What comes next?

The PCI-SIG will study the requirements of its members and of the industry for the next generation of the PCIe architecture following the successful release of the PCIe 3.0 specifications. Higher signaling rates depend on a number of factors. The PCI-SIG is committed to delivering the most robust and high-performance I/O interconnect specifications, while at the same time maintaining an uncompromised focus on low cost, low power, high volume manufacturability and compatibility, by taking advantage of breakthroughs in signaling technologies and silicon process capabilities.

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Section 7.8.6 - Is the L1 Exit Latency in the Link Capabilities register only the ASPM L1.0 exit latency or does it include the added ASPM L1.2 to ASPM L1.0 latency?

The ASPM L1 Exit Latency in the Link Capabilities register indicates the L1/L1.0 to L0 latency, and does not include added latency due to Clock Power Management, L1.1 or L1.2.

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Why is a new generation of PCIe needed?

PCI-SIG responds to the needs of its members. As applications evolve to consume the I/O bandwidth provided by the current generation of the PCIe architecture, PCI-SIG begins to study the requirements for technology evolution to keep abreast of performance and feature requirements.

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Section 4.2.6.4.1 - When the directed_speed_change variable is changed (as a result of receiving eight consecutive TS1 or TS2 Ordered Sets with the speed_change bit set while in Recovery.RcvrLock), is the eight_consecutive counter cleared and the device does not transition to Recovery.RcvrCfg state at this time?

When setting the directed_speed_change variable (in response to receiving 8 consecutive TS1 or TS2 Ordered Sets with the speed_change bit set), it is recommended, but not required, to reset the counters/status of received TS1 or TS2 Ordered Sets. That is, it is recommended that a Device receive an additional 8 consecutive TS1 or TS2 Ordered Sets with the speed_change bit set after it has started transmitting TS1 Ordered Sets with the speed_change bit set before it transitions from Recovery.RcvrLock to Recovery.RcvrCfg.

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What are the PCIe protocol extensions, and how do they improve PCIe interconnect performance?

The PCIe protocol extensions are primarily intended to improve interconnect latency, power and platform efficiency. These protocol extensions pave the way for better access to platform resources by various compute- and I/O-intensive applications as they interact with and through the PCIe interconnect hierarchy. There are multiple protocol extensions and enhancements being developed and they range in scope from data reuse hints, atomic operations, dynamic power adjustment mechanisms, loose transaction ordering, I/O page faults, BAR resizing and so on. Together, these protocol extensions will increase PCIe deployment leadership in emerging and future platform I/O usage models by enabling significant platform efficiencies and performance advantages.

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Section 4.2.4.2 - When upconfiguring a Link in the LTSSM Configuration.Linkwidth.Start state, are the Lanes which are being activated required to transmit an EIEOS first when they exit Electrical Idle?

No. Lanes being activated for upconfiguration are not required to align their exit of Electrical Idle with the transmission of any Symbol, Block, or Ordered Set type. Furthermore, the Lanes are not required to exit Electrical Idle before the LTSSM enters the Configuration.Linkwidth.Start state.

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Section 6.20 - Is a PASID permitted on a Completion? [refer to Section 6.20 – Lines 8-13 on page 628 of PCIe 3.1]

Section 6.20 – Lines 8-13 on page 628 of PCIe 3.1 states:
A PASID TLP Prefix is permitted on:

- Memory Requests (including AtomicOp Requests) with Untranslated Addresses (See Section 2.2.4.1).

- Translation Requests and Translation Message Requests as defined in the Address Translation Services Specification.

The PASID TLP Prefix is not permitted on any other TLP.

No, the text is correct as-is -- a PASID is not permitted on a Completion.  We will consider if an errata is needed to clarify this.”

 

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What is PCI Express (PCIe) 3.0? What are the requirements for this evolution of the PCIe architecture?

PCIe 3.0 is the next evolution of the ubiquitous and general-purpose PCI Express I/O standard. At 8GT/s bit rate, the interconnect performance bandwidth is doubled over PCIe 2.0, while preserving compatibility with software and mechanical interfaces. The key requirement for evolving the PCIe architecture is to continue to provide performance scaling consistent with bandwidth demand from leading applications with low cost, low power and minimal perturbations at the platform level. One of the main factors in the wide adoption of the PCIe architecture is its sensitivity to high-volume manufacturing materials and tolerances such as FR4 boards, low-cost clock sources, connectors and so on. In providing full compatibility, the same topologies and channel reach as in PCIe 2.0 are supported for both client and server configurations. Another important requirement is the manufacturability of products using the most widely available silicon process technology. For the PCIe 3.0 architecture, PCI-SIG believes a 65nm process or better will be required to optimize on silicon area and power.

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Section 4.2.7.3 - PCIe 3.0 Base spec section 4.2.7.4 states that "Receivers shall be tolerant to receive and process SKP Ordered Sets at an average interval between 1180 to 1538 Symbol Times when using 8b/10b encoding and 370 to 375 blocks when using 128b/130b encoding.ÌÒ For 128/130 encoding, if the Transmitter sends one SKP OS after 372 blocks and a second after 376 blocks, the average interval comes out to be 374 blocks and that falls in the valid range. So is this allowed, or must every SKP interval count fall inside the 370 to 375 blocks?

At 8 GT/s, a SKP Ordered Set must be scheduled for transmission at an interval between 370 to 375 blocks. However, the Transmitter must not transmit the scheduled SKP Ordered Set until it completes transmission of any TLP or DLLP it is sending, and sends an EDS packet. Therefore, the interval between SKP OS transmissions may not always fall within a 370 to 375 block interval.

For example, if a SKP Ordered Set remains scheduled for 6 block times before framing rules allow it to be transmitted, the interval since the transmission of the previous SKP OS may be 6 blocks longer than normal, and the interval until the transmission of the next SKP OS may be 6 Blocks shorter than normal. But the Transmitter must schedule a new SKP Ordered Set every 370 to 375 blocks, so the long-term average SKP OS transmission rate will match the scheduling rate.

Receivers must size their elastic buffers to tolerate the worst-case transmission interval between any two SKP Ordered Sets (which will depend on the Max Payload Size and the Link width), but can rely on receiving SKP Ordered Sets at a long term average rate of one SKP Ordered Set for every 370 to 375 blocks. The SKP Ordered Set interval is not checked by the Receiver.

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Section 4.2.6.4.2 - According to pg227 of spec, "When using 128b/130b encoding, TS1 or TS2 Ordered Sets are considered consecutive only if Symbols 6-9 match Symbols 6-9 of the previous TS1 or TS2 Ordered Set". When in Recovery.Equalization and if using 128b/130b encoding, is it required that lane/link numbers (symbol 2) match in TS1s to be considered as consecutive or is it need not match?

The Receiver is not required to check the Link and Lane numbers while in Recovery.Equalization.

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Section 7.28.3 - When the maximum M-PCIe Link speed supported is 2.5 GT/s, what will be the Link speed following a reset?

The Link Speed following reset will be the result of Configuration process. During the M-PCIe discovery and Configuration process, RRAP is used to discover M-PHY capabilities, analyze and configure configuration attributes accordingly. Depending on the High speed supported by both components, the Link Speed and Rate Series may get configured for HS-G1, HS-G2 or HS-G3 and RATE A or B respectively. For this particular example Link Speed could be either HS-G1 or HS-G2 depending on the supported Link Speeds of the other Component on the LINK.

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Has there been a new compliance specification developed for PCIe 3.0?

For each revision of its specification, PCI-SIG develops compliance tests and related collateral consistent with the requirements of the new architecture. All of these compliance requirements are incremental in nature and build on the prior generation of the architecture. PCI-SIG anticipates releasing compliance specifications as they mature along with corresponding tests and measurement criteria. Each revision of the PCIe technology maintains its own criteria for product interoperability and admission into the PCI-SIG Integrators List.

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Section 4.2.6.9 - When in the Disabled state the Upstream Port transitions to Detect when an Electrical Idle exit is detected at the receiver. Is an Electrical Idle exit required to be detected on all Lanes?

An Electrical Idle exit is required to be detected on at least one Lane.

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Section 4.2.6.6.1.3 - How can I configure the RC, if permissible, to send 4096 FTS to EP while RC transits out of L0s?

Setting the Extended Synch bit in the Link Control register of the two devices on the link will increase the number of FTS Ordered Sets to 4096, but the Extended Synch bit is used only for testing purposes.

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What is equalization? How is Tx equalization different from Rx equalization? What is trainable equalization?

Equalization is a method of distorting the data signal with a transform representing an approximate inverse of the channel response. It may be applied either at the Tx, the Rx, or both. A simple form of equalization is Tx de-emphasis as specified in PCIe 1.x and PCIe 2.x, where data is sent at full swing after each polarity transition and is sent at reduced swing for all bits of the same polarity thereafter. De-emphasis reduces the low frequency energy seen by the Rx. Since channels exhibit greater loss at high frequencies, the effect of equalization is to reduce these effects. Equalization may also be used to compensate for ripples in the channel that occur due to reflections from impedance discontinuities such as vias or connectors. Equalization may be implemented using various types of algorithms; the two most common are linear (LE) and decision feedback (DFE). Linear equalization may be implemented at the Tx or the Rx, while DFE is implemented at the Rx. Trainable equalization refers to the ability to adjust the tap coefficients. Each combination of Tx, channel, and Rx will have a unique set of coefficients yielding an optimum signal-to-noise ratio. The training sequence consists of adjustments to the tap coefficients while applying a quality metric to minimize the error. The choice for the type of equalization to require in the next revision of the PCIe specifications depends largely on the interconnect channel optimizations that can be derived at the lowest cost point. It is the intent of PCI-SIG to deliver the most optimum combination of channel and silicon enhancements at the lowest cost for the most common topologies.

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Will PCIe 3.0 products be compatible with existing PCIe 1.x and PCIe 2.x products?

PCI-SIG is proud of its long heritage of developing compatible architectures and its members have consistently produced compatible and interoperable products. In keeping with this tradition, the PCIe 3.0 architecture is fully compatible with prior generations of this technology, from software to clocking architecture to mechanical interfaces. That is to say PCIe 1.x and 2.x cards will seamlessly plug into PCIe 3.0-capable slots and operate at their highest performance levels. Similarly, all PCIe 3.0 cards will plug into PCIe 1.x- and PCIe 2.x-capable slots and operate at the highest performance levels supported by those configurations.

The following chart summarizes the interoperability between various generations of PCIe and the resultant interconnect performance level:
   

Transmitter Device Receiver Device Channel  Interconnect Data Rate
8GHz 8GHz 8GHz  8.0GT/s
5GHz 5GHz  5GHz  5.0GT/s
2.5GHz 2.5GHz 2.5GHz 2.5GT/s
8GHz 5GHz 8GHz 5.0GT/s
8GHz 2.5GHz 8GHz 2.5GT/s
5GHz 2.5GHz 5GHz 2.5GT/s

In short, the notion of the compatible highest performance level is modeled after the mathematical least common denominator (LCD) concept. Also, PCIe 3.0 products will need to support 8b/10b encoding when operating in a pre-PCIe 3.0 environment.

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Section 4.2.6 - Table 4-14 says that Receiver Errors should not be reported in the L0s or L1 states. During L1 entry, an Upstream Port's transmitter may be in Electrical Idle while its receivers are not in Electrical Idle. Similarly, a Port's transmitters may be in Electrical Idle for L0s, while its receivers are not in Electrical Idle. In these situations, should the Port report Receiver Errors such as 8b10b errors?

If the receivers are in L0s, Receiver Errors should not be reported. It does not matter whether the transmitters are in L0 or L0s for reporting of Receiver Errors. Section 4.2.6.5 specifies the 3 conditions required for the LTSSM to transition from L0 to L1. Until all of these conditions are satisfied, the LTSSM is in L0 state, and should report Receiver Errors, even if its transmitters are in Electrical Idle.

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Section 4.2.6.4.1 - The specification says to transition from Recovery.RcvrLock to Recovery.RcvrCfg, upon receiving eight consecutive TS1 or TS2 Ordered Sets. If a Port in Recovery.RcvrLock state receives x (where x < 8) number of consecutive TS1 ordered sets and then receives (8 - x) number of consecutive TS2 ordered sets, should it transition to Recovery.RcvrCfg, OR should it wait for receiving 8 consecutive TS2 ordered sets to transition to Recovery.RcvrCfg (basically discarding the received TS1 Ordered Sets).

The transition requirements can be satisfied by receiving 8 TS1s, 8 TS2s, or a combination of TS1s and TS2s totaling 8.

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Section 4.2.6.3.1.2 - The question is regarding Configuration.Linkwidth.Start state in the case of upconfiguration. It is written in the spec: "The Transmitter sends out TS1 Ordered Sets with Link numbers and Lane numbers set to PAD on all the active Upstream Lanes; the inactive Lanes it is initiating to upconfigure the Link width; and if upconfigure_capable is set to 1b, on each of the inactive Lanes where it detected an exit from Electrical Idle since entering Recovery and has subsequently received two consecutive TS1 Ordered Sets with Link and Lane numbers, each set to PAD, in this substate." It is not mentioned here if sending of these TS1s should be done ONLY on lanes that detected a receiver in the last time the LTSSM was at Detect state. Is it so?

The only lanes that can be part of an upconfigure sequence are lanes that were part of the configured link when configuration was performed with LinkUp = zero, and Lanes that failed to detect a Receiver can not be part of that initially configured Link. Therefore, a Port in the Configuration.Linkwidth.Start state must only transmit TS1s on a subset of the Lanes that detected a Receiver while last in the Detect state, regardless of if it is attempting to upconfigure the Link width, or not.

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Section 8.4.2 - A switch Upstream port receives a Memory Read TLP while in the D3hot State. The Upstream port handles the received Memory Read Request as Unsupported Request. Is the switch Upstream port allowed or required to send a Completion with Completion Status as UR. Or must it transmit the Completion only after the power state is programmed to D0.

The Completion with UR status is required to be transmitted while the Port is in D3hot, assuming that the Port remains powered long enough to transmit the Completion.

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Is PCIe 3.0 more expensive to implement than PCIe 2.x?

PCI-SIG attempts to define and evolve the PCIe architecture in a manner consistent with low-cost and high-volume manufacturability considerations. While PCI-SIG cannot comment on design choices and implementation costs, optimized silicon die size and power consumption continue to be overarching imperatives that inform PCIe specification development and architecture evolution.

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Section 7.28.3 - The default Target Link Speed field in the Link Control 2 register requires the field be set to the highest support speed. Should the default value of the M-PCIe Target Link Speed Control field be 10b?

The default value of the M-PCIe Target Link Speed Control field is 01b.

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What is scrambling? How does scrambling impact the PCIe 3.0 architecture?

Scrambling is a technique where a known binary polynomial is applied to a data stream in a feedback topology. Because the scrambling polynomial is known, the data can be recovered by running it through a feedback topology using the inverse polynomial. Scrambling affects the PCIe architecture at two levels: the PHY layer and the protocol layer immediately above the PHY. At the PHY layer, scrambling introduces more DC wander than an encoding scheme such as 8b/10b; therefore, the Rx circuit must either tolerate the DC wander as margin degradation or implement a DC wander correction capability. Scrambling does not guarantee a transition density over a small number of unit intervals, only over a large number. The Rx clock data recovery circuitry must be designed to remain locked to the relative position of the last data edge in the absence of subsequent edges. At the protocol layer, an encoding scheme such as 8b/10b provides out-of-band control characters that are used to identify the start and end of packets. Without an encoding scheme (i.e. scrambling only) no such characters exist, so an alternative means of delineating the start and end of packets is required. Usually this takes the form of packet length counters in the Tx and Rx and the use of escape sequences. The choice for the scrambling polynomial is currently under study.

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Section 4.2.6.4.1 - While in the LTSSM Recovery.RcvrLock state, if a Port receives TS Ordered Sets with a Link or Lane number that does not match those being transmitted on at least one Lane, but receives TS Ordered Sets with Link and Lane numbers that match those being transmitted and the speed_change bit is equal to 1b on at least one other Lane, should the Port transition to the LTSSM Recovery.RcvrCfg state or the LTSSM Detect state after a 24 ms timeout?

The Port should transition to the LTSSM Recovery.RcvrCfg state.

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Do PCIe 3.0 specifications only deliver a signaling rate increase?

The PCIe 3.0 specifications comprise the Base and the Card Electro-mechanical (CEM) specifications. There may be updates to other form factor specifications as the need arises. Within the Base specification, which defines a chip-to-chip interface, updates have been made to the electrical section to comprehend 8GT/s signaling. As the technology definition progresses through PCI-SIG specification development process, additional ECN and errata will be incorporated with each review cycle. For example, the current PCIe protocol extensions that address interconnect latency and other platform resource usage considerations have been rolled into the PCIe 3.0 specification revisions. The final PCIe 3.0 specification consolidates all ECN and errata published since the release of the PCIe 2.1 specification, as well as interim errata.

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Section 4.2.3 - Section 4.2.3 states, "After entering L0, irrespective of the current Link speed, neither component must transmit any DLLP if the equalization procedure must be performed, and until the equalization procedure completes." Does that result in the following sequence: 1. Negotiate a Link and enter L0. Do not allow DLLP transmission while in L0. 2. Change the data rate to 8.0 GT/s and execute the equalization procedure. 3. Enter L0. Allow DLLP transmission.

Yes, that is the expected sequence when the autonomous equalization mechanism is executed. Note that Section 4.2.3 also describes other equalization mechanisms.

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Section 4.2.6.4.3 - While down configured and a rate change request occurs, do the unused lanes also participate in the rate change?

The transmitter of the unused lanes remains in Electrical Idle during the speed change.

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Section 5.3.1.4.1 - A Root Port is connected to a multifunction Endpoint. The Root Port is ECRC capable. The multifunction Endpoint only has 1 function that is ECRC capable, the others are not. Software enables ECRC checking and generation in the Root Port and also enables ECRC checking and generation in the 1 Endpoint function that supports it. Given that one function is enabled for ECRC check, is the EP required to check the TD bit & ECRC on all TLPs that target any of the endpoint's functions regardless of whether the receiving function is ECRC capable?

Per Section 2.7.1, the device is required to check ECRC for all TLPs where it is the ultimate PCI Express Receiver. Note that per Section 6.2.4, an ECRC Error is not Function-specific, so it must be logged in all Functions of that device.

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Section 4.2.6.2.3 - Can you please clarify the below statement quoted from section "4.2.6.2.3. Polling.Configuration" of PCI Express 3.0 specification: Receiver must invert polarity if necessary (see Section 4.2.4.4). Does this imply the polarity inversion can only be initiated by receiver in Polling.Configuration state or can the inversion happen in Polling.Active state as well?

When polarity needs to be inverted, it must be done before exiting Poilling.Configuration, which permits it to be done in Polling.Active.

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Does PCIe 3.0 enable greater power delivery to cards?

The PCIe Card Electromechanical (CEM) 3.0 specification consolidates all previous form factor power delivery specifications, including the 150W and the 300W specifications.

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Section 7.11.7 - Software has enabled Virtual Channel VC1 and currently UpdateFC DLLPs for VC1 are being transmitted on the link. Now, software disables VC1. So my question is, should UpdateFC DLLPs for VC1 be transmitted on the link?

When VC Enable for VC1 is set to 0b, the device must stop transmitting UpdateFC DLLPs for VC1.

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What is 8b/10b encoding?

8b/10b encoding is a byte-oriented coding scheme that maps each byte of data into a 10-bit symbol. It guarantees a deterministic DC wander and a minimum edge density over a per-bit time continuum. These two characteristics permit AC coupling and a relaxed clock data recovery implementation. Since each byte of data is encoded as a 10-bit quantity, this encoding scheme guarantees that in a multi-lane system, there are no bubbles introduced in the lane striping process.

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Section 4.2.6.4.4 - Table 4-5 defines that the valid range of Link Number (Symbol 1 of a TS1 Ordered Set) is 0-31 for Downstream Ports that support 8.0 GT/s or above. If a Downstream Port in the LTSSM Recovery.RcvrCfg state receives TS1 Ordered Sets with a Link Number that is not in the range 0-31, do they qualify as "TS1 Ordered Sets ... with Link or Lane numbers that do not match what is being transmitted" ?

Yes. The received Link Number (not in the range 0-31) does not match the transmitted Link Number (in the range 0-31).

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Section 4.2.6.4 - What is the specification condition on transmitting TS1 Ordered sets while in Recover.RcvrLock state?

While the LTSSM is in Recovery.RcvrLock the Transmitter must send TS1 Ordered Sets on all configured lanes continuously with the following exceptions:
1.      At data rates above 2.5 GT/s send an EIEOS every 32 TS1 ordered Sets (4.2.4.2)

  •        EIEOS guarantees that electrical Idle exit will be detected by the link partner

2.      At all data rates send SKPOS according to 4.2.7.3

  •        for clock compensation

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How does the PCIe 3.0 8GT/s "double" the PCIe 2.0 5GT/s bit rate?

The PCIe 2.0 bit rate is specified at 5GT/s, but with the 20 percent performance overhead of the 8b/10b encoding scheme, the delivered bandwidth is actually 4Gbps. PCIe 3.0 removes the requirement for 8b/10b encoding and uses a more efficient 128b/130b encoding scheme instead. By removing this overhead, the interconnect bandwidth can be doubled to 8Gbps with the implementation of the PCIe 3.0 specification. This bandwidth is the same as an interconnect running at 10GT/s with the 8b/10b encoding overhead. In this way, the PCIe 3.0 specifications deliver the same effective bandwidth, but without the prohibitive penalties associated with 10GT/s signaling, such as PHY design complexity and increased silicon die size and power. The following table summarizes the bit rate and approximate bandwidths for the various generations of the PCIe architecture: PCIe architecture Raw bit rate Interconnect bandwidth Bandwidth per lane per direction Total bandwidth for x16 link
PCIe 1.x 2.5GT/s 2Gbps ~250MB/s ~8GB/s
PCIe 2.x 5.0GT/s 4Gbps ~500MB/s ~16GB/s
PCIe 3.0 8.0GT/s 8Gbps ~1GB/s ~32GB/s

Total bandwidth represents the aggregate interconnect bandwidth in both directions.

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Section 7.5.3 - An Endpoint sends a Memory Request Upstream to a Switch. How will the Switch determine if it needs to route that packet Upstream or to an Endpoint below another Downstream Port?

Each Port of a Switch contains registers that define Memory Space apertures. The Memory Base/Limit registers define an aperture for 32-bit non-prefetchable Memory Space. The Prefetchable Memory Base/Limit & their corresponding Upper registers define an aperture for 64-bit prefetchable Memory Space. Here is the basic behavior with a properly configured Switch. If the TLP address falls within the aperture of another Downstream Port, the TLP is routed to that Downstream Port and sent Downstream. If the TLP address falls within a Memory Space range mapped by any BAR within the Switch, the TLP is routed to the Function containing that BAR. Otherwise, if the TLP address falls within an aperture of the Upstream Port, the TLP is handled as an Unsupported Request. Otherwise, the TLP is routed to the Upstream Port where it is sent to the Upstream Link or another Function associated with the Upstream Port.

If a Switch implements and supports Access Control Services (ACS), ACS mechanisms provide additional controls governing whether each Memory Request TLP is routed normally to another Downstream Port, blocked as an error, or redirected Upstream even if its address falls within the aperture of another Downstream Port. See Section 6.12.

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Section 4.2.6.4.3 - When a device has down configured the number of operational lanes, what is the expected power state and characteristics of the unused lanes?

The unused transmitter Lane is put into Electrical Idle. It is recommended that the receiver terminations be left on.

PCI Express - 4.0

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What is the bit rate for the PCIe 4.0 specification and how does it compare to prior generations of PCIe?

Based on PCI-SIG feasibility analysis, the bit rate for the PCIe 4.0 specification will be 16GT/s. This bit rate represents the optimum tradeoff between performance, manufacturability, cost, power and compatibility. PCI-SIG analysis covered multiple topologies. All of these studies confirmed the potential feasibility of 16GT/s signaling with low-cost enablers.

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Why is a new generation of PCIe architecture needed?

PCI-SIG responds to the needs of its members. As applications evolve to consume the I/O bandwidth provided by the current generation of the PCIe architecture, PCI-SIG begins to study the requirements for technology evolution to keep abreast of performance and feature requirements.

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What is PCI Express (PCIe) 4.0? What are the requirements for this evolution of the PCIe architecture?

PCIe 4.0 is the next evolution of the ubiquitous and general-purpose PCI Express I/O specification. At 16GT/s bit rate, the interconnect performance bandwidth will be doubled over the PCIe 3.0 specification, while preserving compatibility with software and mechanical interfaces. The key requirement for evolving the PCIe architecture is to continue to provide performance scaling consistent with bandwidth demand from a variety of applications with low cost, low power and minimal perturbations at the platform level. One of the main factors in the wide adoption of the PCIe architecture is its sensitivity to high-volume manufacturing capabilities and materials such as FR4 boards, low-cost connectors and so on.

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Will PCIe 4.0 products be compatible with existing PCIe 1.x, PCIe 2.x and PCIe 3.x products?

PCI-SIG is proud of its long heritage of developing compatible architectures and its members have consistently produced compatible and interoperable products. In keeping with this tradition, the PCIe 4.0 architecture is compatible with prior generations of this technology, from software to clocking architecture to mechanical interfaces. That is to say PCIe 1.x, 2.x and 3.x cards will seamlessly plug into PCIe 4.0-capable slots and operate at the highest performance levels possible. Similarly, all PCIe 4.0 cards will plug into PCIe 1.x-, PCIe 2.x- and PCIe 3.x-capable slots and operate at the highest performance levels supported by those configurations.

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Will there been a new compliance specification developed for the PCIe 4.0 specification?

For each revision of its specification, PCI-SIG develops compliance tests and related collateral consistent with the requirements of the new architecture. All of these compliance requirements are incremental in nature and build on the prior generation of the architecture. PCI-SIG anticipates releasing compliance specifications as they mature along with corresponding tests and measurement criteria. Each revision of the PCIe technology maintains its own criteria for product interoperability and admission into the PCI-SIG Integrators List.

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What were the requirements outlined for the feasibility analysis?

In assessing potential improvements to the connector, materials, silicon and channel improvements, PCI-SIG required that compatibility, low-cost and high-volume manufacturing be maintained.

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Is PCIe 4.0 architecture more expensive to implement than PCIe 3.x?

PCI-SIG attempts to define and evolve the PCIe architecture in a manner consistent with low-cost and high-volume manufacturability considerations. While PCI-SIG cannot comment on design choices and implementation costs, optimized silicon die size and power consumption continue to be important considerations that inform PCIe specification development and architecture evolution.

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What are the results of the feasibility testing for the PCIe 4.0 specification?

After technical analysis, the PCI-SIG has determined that 16 GT/s on copper, which will double the bandwidth over the PCIe 3.0 specification, is technically feasible at approximately PCIe 3.0 power levels. The preliminary data also confirms that a 16GT/s interconnect can be manufactured in mainstream silicon process technology and can be deployed with existing low-cost materials and infrastructure, while maintaining compatibility with previous generations of PCIe architecture. In addition, the PCI-SIG will investigate advancements in active and idle power optimizations as they become available.

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What are the initial target applications for the PCIe 4.0 architecture?

The PCIe 4.0 specification will address the many applications pushing for increased bandwidth at a low cost including server, workstation, desktop PC, notebook PC, tablets, embedded systems, peripheral devices, high-performance computing markets and more. The target implementations are entirely at the discretion of the designer.

PCI Express - M-PHY

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What is the primary benefit of using PCIe architecture with the MIPI M-PHY?

This collaboration will enable component and device manufacturers to take advantage of the reduction in I/O technology proliferation, allowing them to reduce their product development time, product validation time and significantly increase their time to market. The mobile and handset industry can realize these benefits today by adopting PCIe architecture adapted to run over M-PHY.

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PCIe technology is in every server, workstation and laptop PC. Why is PCIe over M-PHY a suitable I/O technology for tablet and smartphone devices?

As a broadly adopted technology standard, PCIe benefits from several decades of innovations with universal support in all major Operating Systems, a robust device discovery and configuration mechanism, and comprehensive power management capabilities that very few, if any, of the other I/O technologies can match. PCIe technology has a flexible, layered protocol that enables innovations to occur at each layer of the architecture independent of the other layers. In this way, power-efficient PHY technologies, such as MIPI M-PHY, can be integrated with the familiar and highly functional PCIe protocol stack to deliver best-in-class and highly scalable I/O performance in tablet and smartphone devices.

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When and how will the PCI-SIG release the PCIe adaptation layer specification?

The PCI-SIG will deliver this technology as an extension to the existing PCIe 3.0 Base specification via ECN by the end of 2012. This technology will be fully integrated into the next release of the PCIe Base specification, PCIe 4.0, enabling ease of access and reference.

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Is there a name for the PCIe adaptation that operates with the MIPI M-PHY?

The PCI-SIG has recently accepted this technology as a contribution from its members and will soon announce a suitable name for it.

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