PCI-SIG Developers Conference Asia-Pacific Tour 2017 Agenda

Tokyo, Japan
Thursday, October 12, 2017

Time Title
8:00 am - 9:00 am Registration                                                                                                                                          
9:00 am - 10:30 am PCI Express Basics & Background
10:30 am - 11:00 am AM Break and Exhibit
11:00 am - 12:30 pm PCIe 4.0 Electrical Update
12:30 pm - 1:30 pm Lunch and Exhibit
1:30 pm - 2:30 pm PCIe CEM 4.0 Previews
2:30 pm - 3:30 pm PCIe 4.0 Protocol Update
3:30 pm - 4:00 pm PM Break and Exhibit
4:00 pm - 5:00 pm PCIe 4.0 PHY Logical
5:00 pm - 6:00 pm PCIe Compliance Updates

Taipei, Taiwan
Monday, October 16, 2017 – Day 1

Time Title
8:00 am - 9:00 am Registration                                                                                                                                          
9:00 am - 10:30 am PCI Express Basics & Background 
10:30 am - 10:45 am AM Break and Exhibit
10:45 am - 12:15 pm PCIe 4.0 Electrical Update
12:15 pm - 1:15 pm Lunch and Exhibit
1:15 pm - 2:15 pm PCIe CEM 4.0 Previews
2:15 pm - 3:15 pm PCIe 4.0 Protocol Update
3:15 pm - 3:30 pm PM Break and Exhibit
3:30 pm - 4:30 pm PCIe 4.0 PHY Logical
4:30 pm - 5:30 pm PCIe Compliance Updates

Tuesday, October 17, 2017 – Day 2

Time Title
9:00 am - 10:00 am A Comparison of System Latency in Copper and Optical PCIe Links
10:00 am - 10:15 am AM Break & Exhibit
10:15 am - 11:15 am  PCI Express Link Training and Protocol Debug Techniques
11:15 pm - 12:15 pm Performance Tuning PCIe Systems
12:15 pm - 1:15 pm Lunch & Exhibit
1:15 pm - 2:15 pm Many-Channel DMA Virtualization for PCIe-Connected Enterprise SoCs
2:15 pm - 3:15 pm Test and Debug Challenges for PCIe 4.0
3:15 pm - 3:30 pm PM Break and Exhibit
3:30 pm - 4:30 pm A Software Tool for PCIe 4.0 Lane Margining