PCI-SIG Developers Conference 2018 Agenda

The sessions below are categorized by track subject according to the following key:

(1) PCI Express
(2) PCI-SIG Architecture
(3) Members Implementation
(4) Members Implementation

Day One - Tuesday, June 5, 2018
Time Title
8:00 am - 9:00 am
9:00 am - 9:30 am
Registration in Foyer
Introductory Keynote / Annual Members Meeting
9:30 am - 10:30 am (1) PCIe 5.0 Electrical Update    
(2) PCI-SIG Architecture Overview   
(3) Multi-Port Switch for PCI Express  
(4) 32GT/s Channel Design

10:30 am - 11:30 am

(1) PCIe CEM 5.0 Previews
(2) PCIe Cable Update   
(3) PCI Express Link Training and Protocol Debug Techniques 
(4) Analyzing the Real Jitter Performance of an SSC Clock
11:30 am - 1:00 pm Lunch and Exhibit
1:00 pm - 2:00 pm (1) PCIe 5.0 PHY Logical
(2) PCI Express Basics    
(3) Latency in PCIe Expansion Systems
(4) Be Prepared for PHY and PCIe Controller Integration
2:00 pm - 3:00 pm (1) PCIe Compliance Updates  
(2) PCIe Electrical Basics
(3) Implementing Lane Margining in a Heterogeneous System
(4) Trials and Tribulations of Early PCIe 4.0 Adoption
3:00 pm - 3:30 pm PM Break and Exhibit
3:30 pm - 4:30 pm (1) PCIe 5.0 Protocol Update    
(2) M.2 Updates  
(3) Addressing PCIe Test and Debug Challenges with Confidence
4:30 pm - 5:30 pm PCIe Panel Discussion
5:30 pm - 7:00 pm PCI-SIG Evening Reception
Day Two - Wednesday, June 6, 2018
Time Title

 9:00 am - 10:00 am

(1) PCIe 5.0 Electrical Update    
(2) PCIe Form Factor Overview   
(3) PCIe Re-timer in Data Centers Platforms  
10:00 am - 10:30 am AM Break and Exhibit
10:30 am - 11:30 am (1) PCIe CEM 5.0 Previews    
(2) PCIe Cable Update  
(3) 32GT/s Waveform Post Processing vs. Statistical Simulation 
11:30 am - 12:30 pm (1) PCIe 5.0 PHY Logical
(2) PCI Express Basics
(3) Optimal PHY Transceiver Techniques for 16GT/s and Beyond
12:30 pm - 1:30 pm Lunch and Exhibit
1:30 pm - 2:30 pm (1) PCIe 4.0 Compliance Testing Deep Dive
(2) PCIe Electrical Basics
(3) PCIe Range Extension via Robust, Long Reach Protocol Tunnels
2:30 pm - 3:30 pm (1) PCIe 5.0 Protocol Update    
(2) M.2 Updates
(3) Potential Methods for Permitting Connector Resonance at 32GT/s